What Are the Layers of a BCP Board? PCB Stackup Explained
If you searched “what are the layers of BCP board,” start with one correction: BCP board is not the usual electronics term. Most searchers mean PCB, or printed circuit board. The letters have simply been reversed.
The second correction matters more. A PCB does not have one universal list of physical layers. A two-layer rigid board, a multilayer high-speed board, a flex circuit, and a metal-core board use different constructions. And several layers shown in CAD—paste, courtyard, assembly, and mechanical layers—are manufacturing information, not material laminated into the finished board.
Direct Answer: What Are the Layers of a PCB Board?
A typical PCB contains patterned copper conductor layers separated by insulating dielectric material. Its outer surfaces usually receive solder mask, selected copper areas receive a surface finish, and legend ink may be printed above the mask. Multilayer PCBs use laminated cores and prepregs, with plated holes or vias connecting copper layers. Paste and assembly layers are production data, not physical board layers.
1. Separate Physical Layers from CAD Layers
| Layer category | Examples | Present in the finished bare PCB? |
|---|---|---|
| Conductive | Copper signal, power, ground planes | Yes |
| Insulating | Core, prepreg, flexible dielectric | Yes |
| Protective | Solder mask, coverlay | Usually |
| Surface treatment | ENIG, HASL, immersion tin/silver, OSP | On exposed copper only |
| Identification | Legend/silkscreen, permanent marking | Optional physical marking |
| Assembly tooling data | Solder paste apertures, glue data | No; used to make/apply assembly materials |
| Documentation | Assembly drawing, courtyard, fab notes | No |
| Mechanical definition | Profile, slots, cutouts, dimensions | Defines shape; not a material layer |
This distinction solves a common argument: a CAD project may display 20 or more “layers,” while the purchase order calls the product a four-layer PCB. The four refers to copper layers.
2. Read a Typical PCB from Top to Bottom
| Position | Physical feature | Primary job |
|---|---|---|
| Top marking | Legend/silkscreen | Reference designators, polarity, identification |
| Top protective coating | Solder mask | Protects copper and defines exposed soldering areas |
| Top exposed-copper treatment | Surface finish | Preserves solderability/contact surface |
| Top conductor | Patterned copper | Signals, power, ground, component pads |
| Dielectric build | Prepreg/core materials | Electrical isolation and mechanical structure |
| Internal conductors | Copper signal/plane layers | Routing, reference planes, power distribution |
| Bottom conductor | Patterned copper | Signals, power, ground, component pads |
| Bottom finish/mask/legend | Same functional groups as top | Assembly and protection on bottom side |
The surface finish is not normally a full sheet across the board. It is applied to copper left exposed by solder-mask openings, subject to the selected process.
3. Copper Layers Define the Board’s Layer Count
| Board description | Copper structure | What it does not count |
|---|---|---|
| Single-layer PCB | One patterned copper layer | Mask and legend |
| Double-layer PCB | Top and bottom copper | Dielectric core as an extra “layer” |
| Four-layer PCB | Four copper layers | Two masks and two legends |
| Six-layer PCB | Six copper layers | Paste, assembly, and mechanical data |
| Multilayer PCB | Three or more conductive layers laminated together | Every visible CAD layer |
IPC-6012F covers rigid constructions ranging from single- and double-sided boards to multilayers with through, blind, buried, and microvia structures. “Multilayer” says how many conductive layers exist; it does not prescribe one signal/plane arrangement.
4. Assign Every Copper Layer a Job
| Copper-layer role | What it carries | Design concern |
|---|---|---|
| Signal layer | Digital, analog, RF, clocks, buses | Return path, impedance, crosstalk, routing density |
| Ground plane | Reference and return current | Continuity, splits, stitching, noise |
| Power plane | Distributed supply | Plane pairs, current density, decoupling |
| Mixed layer | Signals plus copper regions | Return-path discontinuity and isolation |
| Shield layer | Electric-field containment | Ground connection and edge leakage |
| Heat-spreading copper | Moves heat laterally | Copper balance, connection, isolation |
A plane is still patterned copper. It is not a different raw material simply because most of the layer remains copper-filled.
5. Understand Core and Prepreg
| Material term | State before lamination | Function in finished stack |
|---|---|---|
| Core | Cured laminate, often copper clad | Stable dielectric spacing and structure |
| Prepreg | Resin-impregnated reinforcement not fully cured | Bonds layers and cures during pressing |
| Bonding film | Adhesive dielectric used in selected constructions | Lamination and insulation |
| Flex dielectric | Polyimide or other flexible base material | Flexible insulation and support |
| Coverlay | Flexible dielectric plus adhesive | Protects flex conductors |
| Metal base | Aluminum/copper or other metal structure with dielectric | Mechanical support and thermal spreading |
Prepreg does not press to one guaranteed thickness independent of the design. Glass style, resin content, copper distribution, press cycle, and fill requirements affect the result.
6. Use Dielectric Layers to Control Fields, Not Just Separation
| Dielectric decision | Electrical effect | Manufacturing effect |
|---|---|---|
| Thickness to reference plane | Controls impedance and field containment | Must use available pressed materials |
| Material Dk/Df | Affects propagation and loss | Depends on test method, frequency, and lot |
| Glass weave/resin | Can create local property variation | Influences flow and dimensional behavior |
| Copper roughness interface | Changes conductor loss | Tied to foil/material construction |
| Plane adjacency | Sets return path and interplane coupling | Constrains layer order |
| Insulation requirement | Supports voltage withstand | Requires spacing/material/process evidence |
Do not treat “FR-4” as a complete dielectric specification. It describes a broad family, not one exact Dk, Df, Tg, glass transition behavior, or high-frequency model.
7. Solder Mask Is Not a Copper Layer
Solder mask is a patterned protective coating on the board surfaces. Its openings expose pads, contacts, test points, or other selected copper features.
| Mask feature | Purpose | Common mistake |
|---|---|---|
| Pad opening | Leaves solderable area exposed | Assuming opening equals copper pad size |
| Mask expansion | Adjusts opening relative to feature | Using one value for every fabricator |
| Mask dam/sliver | Separates adjacent openings | Designing below registration/process capability |
| Via treatment | Tented, plugged, filled, or open as specified | Using “tented” and “filled” interchangeably |
| Color/finish | Identification and appearance | Assuming color has no process impact |
| Mask clearance to silk | Protects exposed copper and legibility | Allowing legend to be clipped unexpectedly |
Ucamco’s Gerber specification identifies top and bottom solder-mask files independently from copper and legend. That file distinction mirrors their different manufacturing functions.
8. Surface Finish Covers Selected Exposed Copper
| Surface-finish decision | Why it matters | Ask before selecting |
|---|---|---|
| Solderability | Assembly process and shelf handling | What solder alloy and number of thermal cycles? |
| Planarity | Fine-pitch/BGA paste transfer and joint formation | How fine are the pads? |
| Contact performance | Keys, switches, connectors, probes | Is wear/contact resistance critical? |
| Wire bonding | Bondability and metallurgy | Which wire and bond process? |
| Storage | Oxidation protection and shelf life | Packaging and storage conditions? |
| Thickness/control | Cost and functional performance | Which standard and acceptance limits apply? |
Finish selection is a system decision. A finish suitable for ordinary solder pads may not be correct for edge contacts, wire bonding, or repeated mechanical contact.
9. Legend and Paste Are Very Different “Layers”
| CAD layer | Output purpose | Becomes part of bare board? |
|---|---|---|
| Top/bottom legend | Prints markings and component references | Yes, if ordered and manufacturable |
| Top/bottom paste | Defines stencil apertures | No |
| Assembly outline | Documents component placement | No |
| Courtyard | Reserves assembly/rework space | No |
| Component data | Supports placement/programming | No |
| Fabrication drawing | Defines board requirements | No |
Ucamco defines Legend,Top/Bot separately from Paste,Top/Bot and component data. Never send paste files as if they were solder mask, even though both may look like pad patterns in a viewer.
10. Vias Connect the Copper Stack
| Via type | Layers connected | Main tradeoff |
|---|---|---|
| Through via | Top to bottom, with connections on selected layers | Simple but consumes routing area through full stack |
| Blind via | Outer layer to one or more inner layers | More routing freedom, added process control |
| Buried via | Inner layer to inner layer | Frees outer surfaces, requires lamination sequencing |
| Microvia | Typically shallow laser-drilled interconnect | HDI density with structure/reliability rules |
| Via-in-pad | Via placed in component pad | Often requires fill/cap/planarity control |
| Thermal via | Conductive path used to move heat | Thermal performance, solder loss, and process balance |
IPC has warned the industry about microvia reliability in high-performance products. Do not choose stacked or complex via structures solely because they make routing easier; qualify the build and acceptance plan.
11. Compare Common Stackup Concepts
| Copper count | Example concept, top to bottom | Appropriate when |
|---|---|---|
| 1 | Signal | Very simple, low-density circuitry |
| 2 | Signal / Signal | Simple routing with limited plane control |
| 4 | Signal / Ground / Power / Signal | General digital/analog products |
| 6 | Signal / Ground / Signal / Signal-Power / Ground / Signal | More routing and reference control |
| 8 | Signal and plane layers in a symmetric arrangement | Density, SI/PI, EMI, or power needs justify it |
These are concepts, not universal recipes. High-speed interfaces may require signal layers adjacent to solid reference planes, while mixed-signal and power designs may need different plane and dielectric priorities.
12. Build the Stackup with the Fabricator
| Release item | Minimum information | Why it matters |
|---|---|---|
| Copper order | L1 through final layer with function | Prevents layer inversion and ambiguity |
| Finished thickness | Nominal and tolerance | Mechanical fit and process control |
| Copper requirement | Starting/finished context where applicable | Current, impedance, plating, etch |
| Dielectric construction | Approved material and thicknesses | Impedance, isolation, reliability |
| Via spans | Drill type and connected layers | Defines process sequence |
| Impedance table | Layer, geometry, target, tolerance | Links layout to build |
| Mask/finish/legend | Side, type, color, openings, special marks | Completes outer-board definition |
| Acceptance | Standard, class, coupons, special requirements | Creates a testable procurement package |
Start a PCB stackup engineering review before final routing. A fabricator may suggest a more available core/prepreg combination, but any change must be checked against impedance, finished thickness, via geometry, and mechanical constraints.
13. PCB Layer Release Checklist
| Check | Pass condition | Stop condition |
|---|---|---|
| Terminology | PCB and copper-layer count are explicit | “BCP” or “layers” remains undefined |
| Stack order | Every copper layer is numbered and named | Filename order must be guessed |
| Physical vs tooling data | Mask, legend, paste, and assembly functions separated | Similar-looking files are interchangeable |
| Dielectrics | Approved material/construction recorded | “FR-4” is the entire specification |
| Impedance | Geometry matches released stackup | Old stackup remains in field solver |
| Vias | Spans, drill types, fill/cap requirements defined | Drill data lacks layer connectivity |
| Copper balance | Construction reviewed for symmetry/process | Large uncontrolled imbalance |
| Outer coatings | Mask, finish, and markings are complete | Surface treatment assumed |
| Independent view | Final manufacturing dataset inspected | Native CAD view is the only check |
Frequently Asked Questions
Is BCP board the same as PCB board?
In most search contexts, “BCP board” is a letter-order typo for PCB. BCP can mean other things in unrelated industries, so confirm the context before using it in a technical specification.
How many layers does a PCB have?
A PCB can have one, two, four, six, eight, or many more copper layers. The correct count depends on routing density, power distribution, signal integrity, EMI, thickness, via structure, and cost.
Do solder mask and silkscreen count as PCB layers?
They are physical coatings or markings, but they are not counted in the conventional copper-layer number. A four-layer PCB has four copper layers even if it also has mask and legend on both sides.
Is solder paste a PCB layer?
No. The paste layer in CAD normally defines stencil apertures for assembly. Solder paste is deposited during PCBA production and is not a laminated bare-board layer.
What is a good four-layer PCB stackup?
A common concept is signal / ground / power / signal, but it is not automatically best. Return paths, impedance, plane continuity, power integrity, EMC, copper balance, and available materials must be reviewed through a PCB fabrication and CAM assessment before the stackup is approved.
Final Takeaway
“What are the layers of BCP board?” usually means “What are the layers of a PCB?” The answer begins with copper conductors and insulating dielectrics, then adds solder mask, selective surface finish, and optional legend. Paste, assembly, courtyard, and mechanical layers are manufacturing data rather than laminated materials. Define every file by function, and release the stack only after a PCB manufacturing review confirms materials, vias, impedance, thickness, and acceptance requirements.
