Rogers RT/duroid® 5870 and 5880 are glass-microfiber-reinforced PTFE laminates for low-loss microstrip, stripline, antenna, microwave and millimeter-wave circuits. Their headline numbers are close, but they are not interchangeable line items. RT/duroid 5870 has a process dielectric constant of 2.33 ± 0.02 at approximately 10 GHz, while RT/duroid 5880 is 2.20 ± 0.02. Their 10 GHz dissipation factors are 0.0012 and 0.0009, respectively.
Those values are only the beginning of the selection decision. Copper type, dielectric thickness, trace geometry, plated-hole structure, bonding material and the Dk method used in simulation can move a real board away from a simplified datasheet comparison. QFPCB reviews these variables before treating a stackup as manufacturable.
What are Rogers RT/duroid 5870 and 5880?
Both materials use randomly oriented glass microfibers to reinforce a PTFE matrix. Rogers states that this construction supports dielectric-constant uniformity from panel to panel and across a wide frequency range. The official datasheet lists commercial airline broadband antennas, microstrip and stripline circuits, millimeter-wave applications, military radar, missile guidance and point-to-point digital-radio antennas as typical applications.
The low Dk helps produce wider controlled-impedance traces than a higher-Dk laminate at the same dielectric thickness. The very low Df helps reduce dielectric loss along long RF paths. Neither advantage removes conductor loss, launch discontinuities, connector effects, surface roughness or fabrication variation from the design.
RT/duroid 5870 vs 5880: the practical differences
RT/duroid 5880 provides the lower Dk and lower 10 GHz Df. RT/duroid 5870 has lower published CTE in all three axes and slightly higher thermal conductivity. That creates a real engineering tradeoff: the lowest loss number is not automatically the lowest-risk choice for every plated, thermally cycled or mechanically constrained assembly.
| Decision factor | RT/duroid 5870 | RT/duroid 5880 | Engineering meaning |
|---|---|---|---|
| Process Dk at ~10 GHz | 2.33 ± 0.02 | 2.20 ± 0.02 | 5880 generally produces wider traces for the same impedance and dielectric thickness. |
| Df at 10 GHz | 0.0012 | 0.0009 | 5880 has the lower published dielectric-loss value. |
| CTE X / Y / Z | 22 / 28 / 173 ppm/°C | 31 / 48 / 237 ppm/°C | 5870 has lower published expansion; plated-hole and assembly reliability still depend on the complete construction. |
| Thermal conductivity | 0.22 W/m/K | 0.20 W/m/K | Neither material should be selected as a high-thermal-conductivity solution without a separate thermal path. |
| Best initial fit | Very-low-loss RF with somewhat lower published CTE | Lowest Dk and Df of the pair | Confirm the choice through RF simulation, stackup review and prototype measurement. |
Official RT/duroid 5870 and 5880 datasheet values
Rogers distinguishes process Dk from design Dk. Quality acceptance uses the IPC-TM-650 process measurement, while the design Dk is an average derived from tested lots and common thicknesses. Rogers specifically warns that the process value may not be correct for design purposes, especially for microstrip. For a new RF layout, identify the Dk definition used by the field solver and verify the prototype’s electrical performance.
| Property | RT/duroid 5870 | RT/duroid 5880 | Condition / test method |
|---|---|---|---|
| Process Dk | 2.33; 2.33 ± 0.02 specification | 2.20; 2.20 ± 0.02 specification | 1 MHz: IPC-TM-650 2.5.5.3; ~10 GHz at 23°C: IPC-TM-650 2.5.5.5; C24/23/50; Z direction |
| Design Dk | 2.33 | 2.20 | 8-40 GHz, differential phase-length method; Z direction |
| Dissipation factor, tan δ | 0.0005 at 1 MHz; 0.0012 at 10 GHz | 0.0004 at 1 MHz; 0.0009 at 10 GHz | IPC-TM-650 2.5.5.3 and 2.5.5.5; C24/23/50; Z direction |
| Thermal coefficient of εr | -115 ppm/°C | -125 ppm/°C | -50 to 150°C; IPC-TM-650 2.5.5.5; Z direction |
| Volume resistivity | 2 × 107 MΩ·cm | 2 × 107 MΩ·cm | C96/35/90; ASTM D257; Z direction |
| Surface resistivity | 2 × 107 MΩ | 3 × 107 MΩ | C96/35/90; ASTM D257; Z direction |
| Moisture absorption | 0.02% | 0.02% | 0.062 in (1.6 mm), D48/50; ASTM D570 |
| Thermal conductivity | 0.22 W/m/K | 0.20 W/m/K | 80°C; ASTM C518; Z direction |
| CTE X / Y / Z | 22 / 28 / 173 ppm/°C | 31 / 48 / 237 ppm/°C | 0-100°C; IPC-TM-650 2.4.41 |
| Td | 500°C | 500°C | TGA; ASTM D3850 |
| Density | 2.2 g/cm³ | 2.2 g/cm³ | ASTM D792 |
| Copper peel | 27.2 pli (4.8 N/mm) | 31.2 pli (5.5 N/mm) | 1 oz (35 µm) ED copper after solder float; IPC-TM-650 2.4.8 |
| Flammability | UL 94 V-0 | UL 94 V-0 | Datasheet rating |
| Lead-free process compatible | Yes | Yes | Rogers datasheet declaration |
Standard thickness, panel and copper options
The material callout should include more than “RT5880” or “RT5870.” Rogers asks buyers to specify dielectric thickness and tolerance, copper type and copper weight. A stackup drawing should also identify the required finished copper, surface finish, impedance geometry and bonding material.
| Order item | Official standard options | What to confirm with QFPCB |
|---|---|---|
| Dielectric thickness | 0.005, 0.010, 0.020, 0.031 and 0.062 in (0.127, 0.252, 0.508, 0.787 and 1.575 mm), each with the datasheet tolerance | Exact grade, nominal thickness, tolerance and current material availability |
| Additional thickness range | 0.0035-0.375 in in varying increments | Do not assume every increment is stocked or compatible with the requested panel and copper |
| Standard panel sizes | 18 × 12 in (457 × 305 mm) and 18 × 24 in (457 × 610 mm) | Usable production panel, tooling border, coupon and nesting plan |
| ED copper | ½ oz (18 µm) HH/HH; 1 oz (35 µm) H1/H1 | Copper profile, finished copper and RF-loss impact |
| Rolled copper | ½ oz (18 µm) 5R/5R; 1 oz (35 µm) 1R/1R | Bend, surface roughness and fabrication requirements |
| Other claddings | Heavy metal, resistive foil and unclad configurations may be available | Manufacturer availability and project-specific fabrication review |
Why process Dk and design Dk cannot be mixed
The 2.20 and 2.33 numbers are often copied directly into an impedance calculator without recording the method. That is risky. The process Dk supports material acceptance under a defined clamped-stripline test, whereas a PCB field solver models a specific transmission-line geometry. Copper roughness, resin-to-glass distribution, thickness, frequency and solder mask can change effective behavior.
For a controlled-impedance design, send QFPCB the target impedance, trace type, copper thickness, finished dielectric thickness and tolerance, reference planes, solder-mask requirement and operating frequency. We can then review the proposed PCB layer stackup rather than treating one datasheet cell as a complete model.
PTFE fabrication risks that should be resolved before layout release
RT/duroid 5870 and 5880 are soft PTFE composites, so an FR-4 drill and hole-preparation assumption should not be reused without review. Rogers’ fabrication guide says PTFE smear can form as connected resin flaps and that it should be prevented through controlled drilling rather than assumed removable afterward. Carbide drills, conservative tool life and supported entry/exit materials are part of the process plan.
Hole quality and plating adhesion
The official guide recommends tight control of drill surface speed, feed and tool condition. Hole-wall preparation and activation must be selected for PTFE before electroless copper. For a multilayer or hybrid design, via aspect ratio, finished-hole size, copper requirement and thermal cycling all need project review; the material’s low RF loss does not guarantee plated-through-hole reliability.
Dimensional movement and registration
The published CTE values are much higher in Z than in X or Y, especially for RT/duroid 5880. Routing, copper balance, panel support and lamination construction affect dimensional stability. We therefore review the whole high-frequency PCB build, not only the RF core.
Copper foil is an electrical choice
Electrodeposited and rolled copper are both listed options. At microwave and millimeter-wave frequencies, conductor surface profile can influence insertion loss. The fabrication drawing and simulation record should identify the copper type assumed; changing foil only at purchasing stage may invalidate the loss model.
When to use 5870, 5880 or a hybrid stackup
Choose RT/duroid 5880 when the lower Dk and lower published Df materially help a low-loss RF path, antenna element or broadband structure. Consider RT/duroid 5870 when its 2.33 Dk is suitable and the lower published CTE is valuable. If the design also needs dense digital routing, power distribution or many plated vias, a hybrid construction may reduce cost or improve manufacturability—but introduces bonding, expansion and registration interfaces that must be engineered.
QFPCB supports RT5000-series projects within our high-frequency process window. General capabilities include single- and double-sided boards plus reviewed multilayer or high-frequency hybrid builds; the exact material thickness, copper, panel plan, minimum holes, layer count and bonding system remain subject to engineering confirmation. We do not interpret family-level support as proof that every thickness is in stock.
If your design needs a ceramic-filled PTFE laminate with copper-matched in-plane CTE and a nominal Dk of 3.00, compare these glass-microfiber materials with our Rogers RO3003 PCB material guide. RO3003, RT/duroid 5870 and RT/duroid 5880 are not drop-in substitutes; use the exact datasheet, thickness and RF model required by the design.
Impedance simulation and stackup support from QFPCB
QFPCB can provide stackup impedance simulation, calculation and technical review for multilayer PCB, hybrid PCB and Mechanical Blind Hole PCB. We check the declared Dk method, dielectric thickness, copper geometry, solder mask, reference-plane relationship and manufacturing limits before a stackup is released for quotation.
PCB engineer Alan has more than 10 years of PCB CAM engineering experience. For material and stackup questions, contact [email protected]. Simulation support does not replace prototype RF measurement, and the final impedance and test plan must be agreed for the actual design.
Files to send for an RT/duroid PCB quotation
- Gerber or ODB++ fabrication data and NC drill files
- Layer order, finished board thickness and copper requirements
- Exact material callout: RT/duroid 5870 or 5880, dielectric thickness and tolerance
- Copper type and weight, including the profile assumed in RF simulation
- Controlled-impedance table with trace width, spacing, reference layers and target values
- Bonding material and hybrid-material requirements for multilayer builds
- Finished-hole sizes, via types, aspect ratios and any backdrill details
- Surface finish, outline tolerance, cavity or depth-routing requirements
- RF coupon, TDR or other verification requirements agreed for the project
- Expected prototype and production quantities
Providing these details allows our impedance-control PCB review to identify conflicts before tooling. A material name without thickness, copper and geometry is not enough for a defensible RF quotation.
Frequently asked questions
Is RT/duroid 5880 better than RT/duroid 5870?
Not in every design. RT/duroid 5880 has the lower published Dk and 10 GHz Df, which can help reduce dielectric loss and widen an impedance-controlled trace. RT/duroid 5870 has lower published X/Y/Z CTE and slightly higher thermal conductivity. Select the grade by RF loss, geometry, plated-hole structure, thermal cycling and availability—not by Df alone.
What Dk should I use for RT/duroid 5880?
Use the Dk definition required by your simulation method. Rogers lists a 2.20 ± 0.02 process specification at approximately 10 GHz and a 2.20 design Dk from 8 to 40 GHz. Do not assume these are interchangeable. Record the method, thickness, copper and frequency, then correlate a new design with prototype electrical measurements.
What Dk should I use for RT/duroid 5870?
Rogers lists 2.33 ± 0.02 as the process Dk specification at approximately 10 GHz and 2.33 as the design Dk over 8-40 GHz. The correct model input depends on the transmission-line structure and solver methodology. QFPCB can review your stackup inputs, but the prototype should still be verified for the intended RF response.
Are RT/duroid 5870 and 5880 suitable for millimeter-wave PCBs?
Yes, Rogers lists millimeter-wave circuits among their typical applications and states that the low dissipation factor extends use to Ku-band and above. Performance still depends on copper roughness, trace definition, launches, connectors, surface finish, laminate thickness and fabrication control. Treat material selection as one part of the complete RF channel design.
Can RT/duroid 5880 be used in a multilayer hybrid PCB?
Yes, a reviewed hybrid stackup can combine an RT/duroid RF layer with other compatible materials. The bonding system, lamination temperature, CTE mismatch, registration, via structure and impedance geometry must be evaluated together. QFPCB supports hybrid and multilayer reviews, but the final construction and material availability require project-specific engineering confirmation.
Why is drilling RT/duroid different from drilling FR-4?
The soft PTFE composite can develop re-deposited debris and flap-style smear if drilling is not controlled. Rogers recommends carbide tools, suitable entry and exit materials, conservative stack height and tool life, and defined cutting parameters. Hole-wall activation for plating must also be compatible with PTFE. Reusing an FR-4 drill program without review creates avoidable plating risk.
Does a 500°C Td mean the PCB can operate continuously at 500°C?
No. Td is a thermogravimetric decomposition result under a specified test method, not a continuous operating-temperature rating for a finished PCB assembly. Long-term service temperature depends on the laminate, copper, bonding system, plated holes, components, solder joints, mechanical loading and environmental conditions. Use the application’s thermal and reliability qualification requirements.
What information is required to quote an RT5880 PCB?
Provide the exact grade, dielectric thickness and tolerance, copper type and weight, layer stackup, impedance table, finished thickness, drill data, via structure, surface finish, board outline and quantity. For hybrid or multilayer designs, identify every dielectric and bonding material. These inputs let QFPCB assess material availability, panelization, PTFE processing and test requirements before quotation.
Build an RT/duroid stackup around the real RF requirement
RT/duroid 5870 and 5880 are both strong choices for very-low-loss RF circuits, but the correct decision comes from the complete stackup—not a single Dk or Df value. Send QFPCB your frequency range, impedance requirements, dielectric thickness, copper assumptions, via structure and mechanical constraints. We will review material availability and the manufacturing path before you freeze the layout.
Official references: Rogers RT/duroid 5880 product page, RT/duroid 5870/5880 datasheet, and Rogers fabrication guidelines.
