26L ATE Load Board

ATE Load Board Design

As a test engineer, you must create the design specification that a PCB vendor can use to lay out and manufacture a load board. The complexity of the design will mirror the performance requirements of the DUT—high-speed mixed-signal chips require a much more complex load board than do low-speed digital chips.

Construction

A high-performance load board (Figure 1 ) consists of a PCB with a test socket and any necessary components such as resistors, capacitors, inductors, relays, connectors, and onboard circuits. The PCB laminate is the base material of the load board. The typical laminate is FR4 (the industry-standard Flame Retardant 4 fiber glass); The number of PCB layers varies, but you can expect 20 or more layers for a complex load board (Figure 2 ). Load-board design encom passes three main goals:

• enable testing of the DUT as defined in the test plan,
• minimize distortion of the DUT’s performance,
• and be flexible enough to handle future test needs.

Figure 1. A test socket, shown in close-up in (a), located on the top surface of a load board (b) provides physical and electrical contact to a DUT. (c) Connectors on the bottom of the load board provide the interface to ATE test-head instrumentation.

Figure 2. Load boards can have 20 or more layers of power, signal, and ground conductors.

Fulfilling these goals usually involves some tradeoffs. For example, assume the test plan requires a clock driven to the DUT. You can fulfill the first goal by routing a tester clock source to the DUT clock pin. To fulfill the second, you can minimize the length of this clock routing. But what if someday you need to use a higher performance clock than the tester can provide? You’re out of luck because the clock pin is hard-wired to the tester’s clock source.

To have the flexibility to use any clock source, you could route the clock pin to a connector on the load board instead of to the tester’s clock source. Routing to a connector would fulfill the third goal by maintaining flexibility, but the second goal would suffer because the connector and cabling may degrade the clock path. You must decide whether the flexibility is worth the signal degradation.

Power-supply routing

You should specify that each of the DUT’s power supplies be isolated on its own separate power plane on the load board—even if the DUT requires multiple power supplies with the same nominal voltage. The separate planes provide noise immunity between the supplies and also allow you to independently change any of the power-supply settings. To reduce signal noise coupling to the power supplies, minimize the overlay of power planes and digital signal routing. Add sense lines to allow power supplies to monitor their output voltage and compensate for power-supply noise. Specify that sense lines be connected to the power plane as close to the DUT as possible.

Use decoupling capacitors to filter power-supply noise. These capacitors should be connected between each power plane and ground plane. Power-supply noise has a variety of frequency components based largely on DUT operating frequencies. Choose the number and size of decoupling capacitors that will maximize noise filtering over a range of frequency. A capacitor has maximum decoupling (minimum impedance) at a single frequency known as its resonant frequency; the resonant frequency depends on the size of the capacitor and can be found in capacitor data sheets. To get decoupling over a wide frequency range, you need to use at least three capacitors of different sizes in parallel to overcome the parasitic effects of a resonant tank circuit that the parallel capacitors form. To determine the frequency range you need to decouple, use this equation:

Bandwidth = 0.35 / T_RISE

For example, given a signal rise time of 200 ps, the required decoupling frequency range is 1.75 GHz.

To filter high-frequency noise, select several small capacitors with resonant frequencies spanning the frequency bandwidth. Use a large bulk capacitance to filter low-frequency noise, which often manifests itself as power-supply droop. You can estimate the amount of bulk capacitance, C, you need using this equation:

C = I / (dV/dt)

For example, given I = 2 A (the current change needed by the DUT), dV = 50 mV (the allowable drop in the power supply voltage), and dt = 1 µs (the time needed for the capacitor to supply the current), then the required bulk capacitance is 40 µF.

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Signal routing

A chip’s signals can be categorized as either low-speed digital signals or high-performance signals. The low-speed digital category includes the signals that a tester’s standard digital-channel pin electronics can adequately test. The high-performance category includes signals whose measurements require high-performance instrumentation with more speed or accuracy than the tester’s digital channels can provide.

Not surprisingly, the high-performance signals deserve first priority for your load-board design. You should route them to high-performance instrumentation within the test head or to a connector on the load board, where they will be accessible via cable to any instrument. Keep the trace lengths for high-speed signals as short as possible. Avoid long parallel runs of mixed types of signals to reduce noise coupling. If the signals are differential pairs, then route them in pairs with matched lengths. Expect ±5ps tolerance for matched-length traces. Route the high-performance signals on their own signal planes, separate from the low-speed digital signal planes.

You’ll route low-speed digital signals to the tester’s digital channels. The performance requirements of these pins are relatively low, and the load-board design requirements are more relaxed. The trace lengths for the low-speed digital signals should be matched, but they do not need the tight tolerance of the high-speed signal matching. Expect ±50 ps tolerance across the low-speed digital signals. Route the low-speed digital signals on their own signal planes, separate from the high-performance signal planes.

In some cases, multiple test resources will need access to the same signal. You can route such a signal to a relay or relay tree that can select between the resources, or you can route the signal to a load-board connector for connection via cable to any instrument. The latter approach is more flexible, but it isn’t practical for high-volume testing.

You should route several spare tester digital channels with matched length paths to connectors on the load board. These spare digital channels can serve as triggers, or you can use them to route signals accessible via external connectors directly to test-head instruments.

Be sure to specify the signal trace impedance. Most ATE testing occurs in a 50-V environment. You can measure the actual trace impedance if you design a test trace into each signal layer. These traces should have a connector on each end and be 1-ns in electrical length (or whatever length you have room for, but make sure you know the exact length). You can perform time-domain reflectometry on the test traces to verify the impedance and check for discontinuities.

You can measure PCB loading on DUT drivers if you include test traces of various lengths in the load board. These traces should have connectors at each end. If the DUT has differential drivers, then these load traces should also have a differential configuration.

Connectors and components

Pins that will connect to a cable require that a connector be mounted on the load board. High-speed applications commonly use SMA and SSMB connectors. SMA connectors are screw-on/off and are larger and have higher bandwidth than the push-pull SSMB connectors. SMA connectors also provide a sturdier connection to the load board. The SSMB connection can be bent by the weight and pull of heavy semi-rigid cables.

If you need the extra bandwidth, then choose the SMA. If you need a smaller footprint or prefer the ease of a push-pull connection, then choose the SSMB. Be sure to specify the mating type (plug, jack) of the connector. If the connectors are being placed near the socket in an area that will be covered by a thermal-air-stream chamber, then specify right-angled connectors to allow the cables to lie flat along the load board and not interfere with the thermal chamber being placed over the socket. If you use right-angled connectors, do not place any components in-line that would prevent the cable from attaching horizontally—semi-rigid cables may need several inches of room before they can attain sufficient clearance over adjacent components. Also, space all connectors far enough apart to allow room for cables to be connected to adjacent connectors simultaneously. Each connector should have an identifying text label on the load board.

Place decoupling capacitors as close to the DUT as possible—preferably directly under the socket. Also place AC coupling capacitors and termination resistors as close to the DUT as possible. Use 1% resistors. Components should be surface-mounted whenever possible. Make sure the power supply for the load-board relays has enough strength to power the relays. You can calculate the current draw for each relay by using the following equation:

I_RELAY = V_POWER /R_COIL

The coil resistance can be found in the relay’s data sheets. For calculating worst-case total current draw, assume all relays are on.

Finally, you will need to specify component case size. Case size is the size of the component’s footprint and is the area needed to mount the component on the PCB. Case sizes are given in several ways, such as “case size A,” “0805,” or “0.055x .055 in.” Case size “0805” is an abbreviation for “0.08×0.05 in.” There are no industry standards for case sizes A, B, and so on, so you’ll have to check component manufacturers’ data sheets for exact dimensions. When placing components, take into account the socket latch, load-board reinforcing plates (if any), and production handler (if one will be used), which may prevent components from being placed in some areas.