How much current can a PCB via carry?
PCB via current capacity is not a fixed number of amps per hole. Start with the finished hole diameter, copper wall thickness and conducting length to calculate barrel resistance. Then check voltage drop, power loss and the temperature of the complete power path. A low calculated resistance is useful evidence, but it does not establish an acceptable operating temperature.
Think of a plated through-hole via as a tiny copper pipe connecting board layers. Current travels through the pipe wall, not through the empty center. This guide uses a round, hollow plated through-hole carrying DC. It shows how to estimate its electrical losses and decide what still needs fabrication confirmation or prototype testing.
For example, a hypothetical via with a 0.30 mm finished hole, 25 µm uniform copper wall and 1.60 mm conducting length has about 1.08 mΩ barrel resistance at 20°C using reference copper resistivity. At 2 A, its calculated barrel loss is about 4.32 mW. Neither number means that every 0.30 mm via is approved for 2 A. The calculation and its limits are worked through below.
Which dimensions belong in a via current calculation?
Use the dimensions of the finished copper barrel, not just the drill tool size or the visible pad diameter. These are different features, and confusing them can make an apparently precise answer wrong.
| Input | What it means | Where to confirm it |
|---|---|---|
| Finished hole diameter, d | Inner diameter of the copper-lined hole after plating | Fabrication drawing and agreed hole tolerances |
| Wall thickness, t | Copper thickness measured radially through the barrel wall | Specified minimum wall plating and agreed inspection evidence |
| Conducting length, L | Length of barrel carrying the current between the relevant layer connections | Approved stackup and current entry/exit layers |
| Current, I | Continuous DC load for this example; distinguish peak and RMS for other waveforms | Load specification, including startup and fault behavior |
| Allowed drop and temperature | Electrical and thermal limits allocated to this transition | System design requirements, not a calculator default |
The outer diameter of the copper barrel is d + 2t. The copper pad surrounding the hole may be much wider, but that pad is not the cross-section carrying vertical current along the barrel. Likewise, a non-plated mounting hole has no copper barrel and provides no equivalent electrical connection.
Do not enter the board’s “1 oz copper” specification as the via wall thickness. Surface or layer copper weight and deposited hole-wall copper are separate requirements. Also confirm whether a supplier’s drill-file convention represents finished holes or manufacturing drill sizes; do not subtract plating twice.
For an outer-layer-to-outer-layer transition, board thickness is a useful first approximation for L. An inner-layer transition may use a shorter conducting segment. If several layers inject or remove current along one barrel, split the path into segments or use a suitable electrical model. The multilayer PCB stackup defines those connections.
How to calculate via resistance, voltage drop and power loss
Calculate the copper shell area first, then resistance, then the losses at your specified current. Keep the temperature fixed for this initial estimate. This procedure calculates electrical losses; it is not a stand-alone thermal ampacity model.
Step 1: Calculate the copper barrel area
Looking down the via, the conducting copper is the area of the outer circle minus the inner hole:
A = π[(d/2 + t)2 − (d/2)2] = π(dt + t2)
If d and t are in mm, A is in mm2. The approximation A ≈ πdt is useful when the wall is very thin compared with the hole diameter, but the full expression is just as easy to use. Do not use πd2/4: that treats the empty hole as a solid conductor.
For the teaching example, d = 0.30 mm and t = 25 µm = 0.025 mm:
A = π × (0.30 × 0.025 + 0.0252) = 0.02553 mm2.
Step 2: Calculate resistance with consistent units
R = ρL/A, where R is resistance in ohms and ρ is copper resistivity. Using ρ = 0.01724 Ω·mm2/m requires L in meters and A in mm2. The reference value at 20°C comes from the NBS Copper Wire Tables hosted by NIST. Actual deposited copper and operating temperature can differ from this reference.
Here L = 1.60 mm = 0.00160 m:
R = 0.01724 × 0.00160 / 0.02553 = 0.001081 Ω, approximately 1.08 mΩ.
That is the modeled barrel resistance. It excludes resistance where current spreads through pads and planes, plus connectors, traces and other parts of the circuit.
Step 3: Calculate voltage drop and heating power
Use V = IR and P = I2R. At the illustrative load of 2 A:
- Voltage drop: 2 × 0.001081 = 0.002162 V, about 2.16 mV.
- Barrel loss: 22 × 0.001081 = 0.004324 W, about 4.32 mW.
At 5 A, the same fixed-temperature model gives 5.40 mV and 27.0 mW. Increasing current from 2 A to 5 A multiplies loss by 6.25, not 2.5. These figures describe generated heat; they do not tell you the resulting temperature rise.
Step 4: Repeat with manufacturing limits
If the wall were only 20 µm, with the other example inputs unchanged, the area would become 0.02011 mm2 and resistance about 1.37 mΩ. That is approximately 27% more resistance than the 25 µm example. These thicknesses are illustrative alternatives, not claims about a particular IPC class or QFPCB production minimum.
Use the agreed minimum geometry for a conservative design check. A nominal or average plating value does not describe the thinnest part of every barrel. Copper resistance also increases with temperature, so a room-temperature result needs a hot-operating-condition check before release.
How many parallel vias do you need?
Parallel vias can lower electrical resistance, but the required count must satisfy both the voltage-drop budget and the thermal validation. Dividing total current by an assumed “amps per via” value is only meaningful when that rating and its operating conditions are already justified.
For N identical barrels with equal current sharing, Rarray = Rvia/N and each carries I/N. Consider an author-chosen requirement of 5 A with no more than 5 mV allocated to the via transition:
- The resistance budget is 0.005 V / 5 A = 1 mΩ.
- One example barrel at 1.08 mΩ already exceeds that budget before pad and plane losses.
- Two ideal identical barrels in parallel give about 0.540 mΩ, 2.70 mV drop and 13.5 mW total barrel loss at 20°C.
Two is the idealized minimum from this electrical calculation, not the approved production via count. Routing resistance, geometry tolerances, hot resistance, unequal sharing and the measured thermal result may require a different design.
Current divides according to the resistance of the complete branches. A via reached through a short, wide connection may carry more than one reached through a long, narrow connection. Count only vias on the correct net and connected between the required layers. Check the copper feeding the array, thermal-relief spokes, plane clearances and the return path. A generous array cannot compensate for a narrow shared neck before it.
Where routing is constrained, a PCB design review should examine the entire transition rather than only enlarging holes. More vias also consume routing and plane area; increasing the count indefinitely is not a universal improvement.
Why a low resistance does not prove an acceptable temperature
Resistance tells you how much heat is generated at a given current. Temperature also depends on where that heat can go and how hot the surrounding board already is.
A barrel connected to broad copper can exchange heat with that copper; a nearby power component can also heat the same region. Board construction, connected planes, ambient temperature, airflow and enclosure conditions change the result. Altium’s discussion of via heating illustrates why the relationship between trace and via temperature depends on geometry. Do not turn a result for one layout into a universal current rating.
A via-current calculator is useful for initial sizing, provided you check its assumptions:
- Does “diameter” mean finished inner diameter, drill diameter or another dimension?
- Is the model a trace-current equation applied to equivalent barrel area, or a board-specific thermal model?
- Does the tool assume equal current sharing across an array?
- Does it distinguish ambient temperature from allowed rise above ambient?
- Which effects are omitted, such as nearby component heat and pad/plane geometry?
An IPC label on a calculator is not proof that the finished board has been tested or complies with every relevant requirement. Record the tool version or calculation date and its stated model. For this article’s hand calculation, there is no thermal resistance model, so no temperature rise is claimed.
Using heavy copper PCB construction changes the layer design, but does not by itself specify the copper thickness inside the holes. Review those two requirements separately.
How to check a via array on a prototype
Validate the transition at the actual operating load and worst intended thermal conditions, using acceptance limits defined before the test. Do not increase current until a board burns to discover its “rating.”
The following sequence is for a suitably protected, isolated low-voltage prototype. Mains-connected equipment, high-energy batteries and safety-critical products need qualified test procedures and protection beyond this guide.
- Prepare the evidence. Record board revision, stackup, finished hole specification, minimum plating requirement, via count and current path. Mark the exact voltage-sense locations. Set maximum allowed drop, temperature and stop conditions.
- Check connectivity before power. Confirm the vias connect the intended layers and nets. A continuity beep can reveal an open connection, but it cannot establish milliohm resistance or acceptable current capacity.
- Measure the intended segment. For an isolated, unpowered resistance measurement, use suitable four-wire equipment when milliohm accuracy is needed. Keithley’s Kelvin measurement note explains how separate current and voltage leads reduce lead-resistance error. Parallel paths on a populated board can still prevent the reading from representing one barrel.
- Apply controlled load. Use a current-limited supply and appropriate load/protection. Increase only within the planned operating range. Measure current and voltage drop across the same defined transition, including the relevant feed copper when that is part of the allocated budget. Do not use an ohmmeter on an energized circuit.
- Observe temperature to stabilization. Record ambient, enclosure and airflow conditions, nearby component loading and the measurement method. A surface temperature does not directly reveal the hottest point inside a barrel; use a suitable sensor arrangement or a validated thermal model when the margin is small.
- Compare and investigate. A drop above budget or temperature above the approved limit fails this test. Unexpected hot spots, rising drop or unequal heating require investigation of current sharing, connections and fabrication quality. Stop on abnormal behavior rather than treating it as more test data.
A successful load test on one prototype is evidence for that sample and setup. Production acceptance, thermal cycling and application-specific reliability requirements remain separate decisions.
What must the fabricator confirm before release?
The fabricator needs an unambiguous construction request, not just “make the vias carry 5 A.” Send the geometry, electrical requirements and evidence expectations together.
- Gerber or agreed manufacturing data, drill files, fabrication drawing and board revision.
- Stackup, finished thickness, current entry/exit layers and the relevant power nets.
- Finished hole diameter and tolerance, plus required minimum copper wall thickness and its acceptance basis.
- Via count, placement, pad/plane connections and any filling, capping or tenting requirements.
- Continuous current, relevant peak/pulse conditions, ambient range, voltage-drop budget and temperature limit.
- Requested evidence, such as agreed microsection/coupon reporting, plus the prototype test plan and any applicable reliability requirements.
Ask which requirements are included in the quotation and which require a different construction or inspection plan. A top-view photograph cannot verify internal plating thickness. Similarly, a cross-section sample provides local structural evidence, not an automatic current rating for every power path.
Via current calculation worksheet
Save this worksheet with the design revision. Its purpose is to show which decisions are supported and which remain open, so another engineer or buyer can review the same assumptions.
| Record | Teaching example | Release check |
|---|---|---|
| Finished hole / wall / length | 0.30 mm / 0.025 mm / 1.60 mm | Replace with approved minimum geometry and actual layer span |
| Barrel copper area | 0.02553 mm2 | Use hollow-shell area, not solid hole area |
| Reference resistance | 1.08 mΩ per barrel at 20°C | Account for temperature and omitted path resistance |
| 2 A single-barrel calculation | 2.16 mV; 4.32 mW | Not a 2 A thermal rating |
| 5 A, two ideal parallel barrels | 2.70 mV; 13.5 mW total | Verify sharing and remaining voltage-drop margin |
| Temperature result | Not calculated | Model or measure the actual board/environment |
| Release evidence | Not supplied by this example | Fabrication agreement, prototype results and reviewer approval |
PCB via current capacity FAQ
Can I assume 1 A per via?
Only as a preliminary project-specific heuristic if its geometry and thermal conditions are justified. “One via” does not define hole size, minimum copper wall, layer connections or ambient conditions. Use the actual construction and verify the complete current path before treating any current as an approved limit.
Does a larger hole always solve the problem?
At fixed wall thickness, a larger finished diameter increases copper barrel area and reduces its modeled resistance. It can also consume pad and routing space. If a shared neck, thermal-relief spoke or connector is the limiting element, enlarging the hole alone will not fix that bottleneck.
Can I use the same calculation for microvias?
Not without adapting the geometry and validating the construction. A microvia can be tapered or copper-filled, and stacked structures introduce interfaces that the simple hollow through-hole model omits. Use the actual build, electrical model and agreed reliability qualification rather than substituting a small diameter into this example.
Does solder or resin filling increase the current rating?
Do not assume a fill creates a solid copper conductor. Nonconductive resin is not an added electrical path. A conductive fill, solder fill or copper-filled construction needs its own material and connection model. Keep the guaranteed barrel copper requirement explicit and have the actual construction reviewed.
Are thermal vias automatically parallel power vias?
No. Check their electrical net and layer connections. Vias intended to spread heat may connect to ground or another designated pad rather than the power net you are sizing. Only count paths that actually carry the specified current between the required nodes.
Should I use peak or RMS current?
For this DC example, the current is constant. For varying current, RMS helps describe resistive average heating when resistance is approximately constant. Peak amplitude, duration and repetition still matter for transient temperature and voltage drop. A continuous-DC estimate does not qualify surge or fault-current behavior.
Does a continuity test prove enough plating?
No. It may detect an open path, but an electrically continuous barrel can still differ from the required geometry or reliability condition. Combine the agreed fabrication acceptance evidence with appropriate electrical and thermal verification. A continuity beep is not a wall-thickness measurement.
Why do two via calculators give different answers?
Compare diameter definitions, plating thickness, units, thermal equations, temperature assumptions and parallel-via treatment. Some tools apply a trace model to barrel area; others add correction factors. Preserve each tool’s assumptions instead of averaging its amp results. Recalculate resistance independently, then validate the thermal decision.
Preparing a power-board fabrication request? Send your stackup, drill data, power-net requirements, via construction and voltage/temperature limits through QFPCB’s contact page. Request confirmation of the finished-hole and minimum-plating requirements, along with the inspection evidence needed for your design. Keep the prototype calculation and test record with the same board revision.
