Frequency, Rise Time and Skew Answer Different Questions
PCB trace length matching should follow the interface’s timing and skew requirements, not a universal frequency threshold. Frequency tells you how often a signal repeats. Rise time describes how quickly an edge changes. Skew is the difference in arrival time between signals that need a defined timing relationship. These quantities are related, but none can simply replace the others.
Think of two messages that must arrive together. Their repetition rate does not tell you how much delivery-time difference the receiver allows. On a PCB, the receiver’s requirements and the complete signal paths determine that allowance.
TI’s High-Speed Layout Guidelines explains that edge rise and fall times influence high-frequency content. A clock with a modest repetition rate can still have fast edges. That is why “only 10 MHz” is not enough information to dismiss transmission-line behavior. Conversely, recognizing fast edges does not tell you that every net must be matched to the same length.
| Input | Question it helps answer | What it does not establish alone |
|---|---|---|
| Clock frequency or data rate | How often does the interface transfer or sample information? | The PCB mismatch allowance |
| Rise/fall time at the relevant load | How abrupt is the transition, and how much signal-integrity attention is needed? | The receiver’s complete timing budget |
| Allowed skew or setup/hold requirements | What relative arrival timing must be maintained? | How much of that budget is still available to the PCB |
| Stackup and path model | What delay does this physical route introduce? | Whether the interface will pass all electrical requirements |
Start by finding the relevant device/interface routing guide. Write down the signals being compared, the allowed mismatch and whether the limit includes package delays. If that information is missing, the next action is a timing review, not arbitrary serpentine routing.
Convert an Available Skew Budget into a Length Tolerance
Use a delay calculation only after establishing what portion of the timing budget belongs to the PCB. For comparable routes on the same transmission-line structure, a useful first-order relation is:
PCB delay mismatch = route-length difference x delay per unit lengthAllowable length difference = available PCB skew / delay per unit length
Keep the units consistent. If delay is expressed in ps/mm, divide picoseconds by ps/mm to obtain millimeters. This simple model assumes the compared paths have similar propagation behavior; it is not a substitute for extraction when layers, vias, packages or discontinuities differ significantly.
A worked example, not an interface specification
Assume an engineering review allocates a total 100 ps relative-arrival allowance to a particular group. For this hypothetical planning exercise, 25 ps is reserved for package mismatch, 15 ps for another identified uncertainty and 20 ps for margin. These are invented teaching inputs, not recommended values for DDR, USB or any other interface.
| Budget item | Example value | Evidence needed in a real design |
|---|---|---|
| Total allowed difference | 100 ps | Applicable interface timing analysis |
| Package contribution reserved | 25 ps | Device/package model or vendor guidance |
| Other identified uncertainty | 15 ps | Documented source and allocation |
| Engineering margin | 20 ps | Approved design margin policy |
| Remaining PCB allowance | 40 ps | 100 – 25 – 15 – 20 |
Suppose the approved stackup model gives 6.5 ps/mm for both compared routes. The example allowance is 40 / 6.5 = 6.15 mm. A 4 mm difference contributes approximately 26 ps; an 8 mm difference contributes approximately 52 ps. The first fits this simplified PCB allocation; the second does not.
This does not prove that the first board works. It checks one requirement under stated assumptions. A real analysis may need signed early/late arrival cases rather than a simple subtraction of absolute allowances. Do not deduct the same package or uncertainty contribution twice if the vendor’s published PCB limit already accounts for it.
TI also shows that propagation depends on the transmission-line environment. Equal physical length on different structures need not produce equal delay. For example, two hypothetical 50 mm routes modeled at 6 and 7 ps/mm differ by 50 ps even though a ruler would call them equal. Confirm the PCB layer stackup before trusting a calculator’s generic material defaults.
Which Signals Belong in the Same Matching Group?
Match signals that have a specified timing relationship. Do not collect unrelated nets into one group just because they connect to the same processor. A constraint with the wrong scope can make a board harder to route without making it more correct.
| Signal relationship | Review focus | Common mistake |
|---|---|---|
| Two members of a differential pair | Allowed within-pair skew and channel requirements | Matching pair totals while ignoring imbalance inside each pair |
| Data associated with a strobe | The specific data/strobe group and device routing rules | Matching the entire bus to one unrelated longest signal |
| Several clock destinations | Specified arrival relationship at the intended endpoints | Ignoring output, package or loading differences |
| Independent control signals | Each signal’s actual timing and integrity requirements | Adding matching sections merely for visual uniformity |
A series resistor can divide a schematic path into multiple named nets. Review the complete relevant path from source to receiver, not only the segment that happens to carry a familiar name. Document the endpoints in the constraint record so a second engineer can reproduce the measurement.
Altium’s official length-tuning documentation distinguishes a matched-length constraint from an overall length constraint and explains scoping constraints to selected nets or signal paths. That distinction matters: two equally long routes can both violate a maximum delay or length requirement.
A Practical Routing and Verification Workflow
Define the requirement before tuning copper. The following sequence is a review method, not a version-specific CAD command recipe.
1. Record the timing relationship and its source
For each group, list the device part numbers, interface mode, source and destination pins, requirement document and limit. Separate within-pair skew from between-pair or data-to-strobe requirements. Stop if the reference does not apply to the actual interface configuration.
2. Approve the path model
Record the stackup revision and the routing layers used by each signal. Identify whether the selected CAD calculation includes package and via contributions. A tool’s displayed delay is meaningful only when its inputs and exclusions are understood. Ask for clarification rather than treating an empty package field as measured zero delay.
3. Route cleanly before adding compensation
Place related devices sensibly and avoid unnecessary detours. Preserve the required reference environment and spacing. If the longest route became long because placement was poor, reconsider placement before extending every other route to match it.
4. Tune only the paths that fail a justified constraint
Apply the correct group and tolerance, then inspect the resulting geometry. Tightly packed tuning sections can create additional coupling; a length number alone does not qualify the structure. For demanding channels, validate the electrical behavior with the appropriate extraction or simulation process instead of assuming every added millimeter creates the expected delay.
5. Recheck after final changes
Repeat constraint checks after layer changes, component movement, fanout edits and manufacturing-driven stackup revisions. Save a report containing actual values, limits and assumptions. A green CAD status says the configured rule passed; it does not certify that the rule was correct or that the hardware meets the complete interface specification.
When the budget is tight or the model is uncertain, move to a signal-integrity review with the relevant device and interconnect models. Prototype validation should follow the interface’s measurement requirements. An ordinary continuity check cannot establish picosecond skew.
What Should Go into the Design and Fabrication Handoff?
Provide enough information for another person to distinguish a timing requirement from a drawing preference. Use this checklist with a PCB design review or fabrication discussion:
- Board and stackup revisions, material construction and relevant routing layers.
- Signal groups with explicit source/destination endpoints.
- Applicable interface/device guidance and the operating mode.
- Skew and overall path limits, including units and whether packages/vias are included.
- Constraint reports showing actual values, not only pass/fail colors.
- Controlled-impedance requirements and the agreed manufacturing verification plan.
- Unresolved exceptions and the person responsible for approving them.
Keep responsibilities clear. Fabrication review can confirm whether the proposed construction and geometry are manufacturable; it does not automatically validate the receiver’s timing budget. An impedance coupon result is not proof that every functional signal path has the correct delay.
Send the stackup, routing constraints and fabrication package through QFPCB’s contact page to request review of manufacturing assumptions and any proposed construction changes. Ask which changes require the design team to rerun timing checks before production approval.
Frequently Asked Questions
At what frequency is PCB length matching mandatory?
There is no universal threshold. Use the interface’s timing relationship and allowed skew, while evaluating edge-rate-related signal integrity separately.
Does lower clock frequency remove all routing concerns?
No. The output edge can remain fast even when repetition rate is reduced. Check the actual driver behavior and interconnect.
Is equal length the same as equal delay?
Only approximately for sufficiently comparable paths. Different routing structures or unaccounted path contributions can change arrival time.
Should every differential pair match every other pair?
Only when the interface requires that relationship. Within-pair and between-pair limits are different constraints.
Can I use 6.5 ps/mm for every board?
No. It is an assumed teaching value here. Obtain a suitable model for the actual stackup and routing structure.
Should I add length to a route that already passes?
Not just to make the layout look symmetric. Additional routing should serve a documented requirement and remain electrically acceptable.
Does passing DRC prove the timing is correct?
No. It proves compliance with the rules the tool checked. Incorrect groups, missing model inputs or unsuitable limits can still produce a misleading pass.
What should I do if the device guide and CAD report disagree?
Compare units, endpoints, group scope and included delays first. Resolve the difference with the responsible design engineer before releasing fabrication files.
