What is Impedance Control PCB
In the context of PCB design, Impedance Control PCBrefers to regulating the impedance of signal traces on the board. At high frequencies, the traces on a PCB behave like transmission lines, and each point along the signal trace has an impedance associated with it. Any variation in impedance between different points can cause a signal reflection, which distorts the original signal, potentially causing errors in data transmission.
Types of PCB Transmission Lines Requiring Impedance Control
In high-speed PCB design, maintaining precise impedance control is critical to ensuring signal integrity and system stability. Various transmission line structures require impedance control to minimize signal reflection, crosstalk, and loss. The key types of PCB transmission lines that demand impedance control include:
Single-Ended Microstrip
A single-ended microstrip is a signal trace routed on the outer layer of a PCB, with a reference ground plane beneath it. Due to its exposure to air, the effective dielectric constant is lower, and impedance control is essential to maintaining consistent signal performance. Common impedance values: 50Ω, 75Ω.
Single-Ended Stripline
A single-ended stripline is embedded within the PCB between two ground planes, providing better shielding and reduced electromagnetic interference (EMI) compared to microstrip. However, it has higher dielectric loss, requiring precise impedance control. Common impedance values: 50Ω.
Microstrip Differential Pairs
Microstrip differential pairs consist of two parallel traces on an outer PCB layer that carry equal and opposite signals. The surrounding environment and spacing between traces significantly impact impedance, making accurate control crucial. Common differential impedance values: 90Ω, 100Ω.
Stripline Differential Pairs
Stripline differential pairs are routed between two reference planes within the PCB, offering superior EMI control. These require highly precise impedance tuning due to the impact of dielectric thickness and copper trace width. Common differential impedance values: 90Ω, 100Ω.
Embedded Microstrip
An embedded microstrip is similar to a standard microstrip but partially enclosed by dielectric material, providing better shielding while still being influenced by surface variations. Precise control of dielectric thickness and material properties is necessary for maintaining impedance stability.
Coplanar Transmission Lines (Single-Ended & Differential)
Coplanar structures have signal traces flanked by ground or power planes on the same PCB layer, enhancing signal integrity and reducing crosstalk. These can be either single-ended or differential, and require precise impedance control based on trace width, spacing, and dielectric properties.
Why is PCB impedance control essential?
For high-speed digital applications, impedance control is a critical factor in ensuring reliable and high-performance signal transmission. In industries such as RF communications, telecommunications, high-speed computing (using signals above 100MHz), high-speed signal processing, and high-quality analog video (e.g., DDR, HDMI, Gigabit Ethernet), precise impedance control is key to high-speed circuit performance.
In high-speed circuits, such as systems used in DDR memory, HDMI video transmission, and Gigabit Ethernet, these signal distortions can be severe enough to prevent the signal from performing its required function. This can result in system failure, data corruption, or performance degradation. Therefore, to ensure accurate, high-quality signal transmission, uniform and controlled impedance of PCB traces is critical.
Why is impedance important in high-frequency circuits?
As high-frequency signals propagate along PCB traces, their impedance is an important consideration for signal integrity. If the impedance changes from one point to another, the signal may reflect, resulting in a mismatch between the transmitted and received signals. The greater the impedance difference, the greater the reflection. This reflected signal propagates in the opposite direction, interfering with the main signal. As a result, the original signal may be distorted, causing communication errors.
Factors Affecting PCB Impedance Control
The factors that mainly affect the impedance of PCB traces include: the width of the copper trace, the thickness of the copper trace, the dielectric constant of the material, the thickness of the dielectric, the thickness of the pad, the copper plating in the through hole, and the solder mask ink.
Copper Trace Width: The width of the copper trace directly influences the impedance. Wider traces result in lower impedance, and narrower traces increase impedance.
Copper Trace Thickness: Thicker copper traces also reduce impedance, while thinner traces increase it.
Dielectric Constant: The dielectric material surrounding the traces (such as FR4 or other materials) plays a key role in determining the trace impedance. Different materials have different dielectric constants, which can affect the propagation speed of the signal and, consequently, the impedance.
The materials that QFPCB factories often have on hand include high-speed board material FR-4 (εr: 3.2-4.8) and high-frequency laminates (εr: 2-16).
Dielectric Thickness: The thickness of the dielectric layer between the signal trace and the reference plane impacts the trace’s impedance. Thicker dielectric layers generally result in higher impedance.
Pad and Via Design: The thickness of pads and vias, as well as how they are plated with copper, can also affect impedance. Improperly designed pads or vias can cause significant impedance variations.
Vias connect traces between layers, can introduce unwanted inductance and capacitance, affecting impedance. Careful via placement and size optimization are crucial for maintaining consistent impedance throughout the trace length.
Solder Mask: The application of solder mask ink over the traces can impact impedance, particularly if the solder mask layer is thick or unevenly applied.
Layer Stackup Design
The arrangement of the layers in a multilayer PCB, known as the stackup, is designed to control impedance. The placement of signal layer and reference ground and power planes is critical. By strategically placing ground planes and power planes around the signal layer can control the distribution of the electric field and achieve the desired impedance.
Challenges of ±10% Impedance Control in High-Precision PCB Manufacturing
In high-speed digital and RF circuit design, precise impedance control is crucial. The signal transmission characteristics in a PCB (Printed Circuit Board) are directly affected by impedance matching. If the impedance deviation exceeds the ±10% tolerance range, it can lead to serious issues such as signal integrity degradation, data transmission errors, and system instability.
The Impact of Impedance Control on Signal Integrity
Poor impedance control can cause several issues, including:
- Signal Reflection: When a signal propagates along a transmission line, any impedance mismatch can cause part of the signal to be reflected, distorting the waveform and affecting signal decoding at the receiver end.
- Increased Crosstalk: Impedance deviation can enhance coupling effects between adjacent signal traces, negatively impacting signal quality.
- Timing Errors: Impedance mismatch can affect signal propagation delay, making high-frequency data transmission timing unstable, potentially violating timing constraints and affecting system functionality.
- Signal Attenuation: Poor impedance matching can lead to energy loss in high-frequency signals, reducing signal amplitude and increasing the bit error rate (BER).
In high-speed signals (>1Gbps) and RF circuits (such as 5G, Wi-Fi 6, and millimeter-wave radar), impedance deviation can cause significant problems. For example, in PCIe 4.0/5.0 transmission rates (16Gbps~32Gbps), even a 5% impedance deviation can increase insertion loss by more than 0.5dB, reducing system transmission performance.
Challenges of Achieving ±5% Impedance Control
Currently, industry standards require impedance control to be within ±10%, but for high-performance circuits such as server motherboards, 5G communication equipment, high-speed network switches, and millimeter-wave radar, the required impedance control accuracy has tightened to ±5% or even stricter. Achieving this level of precision requires the following key technologies:
Advanced Material Control
- Using low-loss, high-stability substrates (such as Rogers 4350B, Isola Tachyon 100G, Panasonic Megtron 6) to minimize variations in dielectric constant (Dk) and dielectric loss (Df), ensuring impedance stability.
- Precisely controlling copper thickness (e.g., 18µm, 35µm) and dielectric layer thickness to prevent processing tolerances from affecting impedance.
- Applying high-precision resin filling technology to ensure uniform dielectric thickness after lamination.
Precision Manufacturing Processes
- Using high-precision Laser Direct Imaging (LDI) technology to refine impedance traces and minimize etching errors.
- Implementing advanced lamination control techniques to ensure uniform dielectric thickness and avoid local thinning or thickening.
- Employing precision electroplating and etching control to maintain consistent copper thickness and minimize impedance deviation.
Rigorous Quality Testing
- Time Domain Reflectometry (TDR) measurement: Measures the characteristic impedance of PCB transmission lines with an accuracy of ±2%.
- Vector Network Analyzer (VNA) testing: Suitable for RF PCBs, providing higher frequency S-parameter measurements.
- Automatic Thickness Detection (ATD): Ensures consistency in copper thickness and dielectric layer thickness.
QFPCB’s High-Precision Impedance Control (±5%)
As a leading high-end PCB manufacturer, QFPCB offers the following key advantages in impedance control:
- Precision Material Management: Strict control of copper foil thickness and dielectric constant (Dk), using high-end substrates to ensure long-term stability.
- High-Precision Manufacturing Equipment: Using LDI photolithography, precise lamination control, and optimized electroplating uniformity to minimize manufacturing errors.
- Advanced Impedance Testing Systems: Equipped with high-precision TDR and VNA testing instruments to ensure every batch meets the ±5% impedance tolerance requirement.
- Strict Process Control System: Full-process quality tracking, including material inspection, production monitoring, and final product testing to ensure consistency.
The requirements for PCB impedance control accuracy are getting higher and higher. The traditional ±10% impedance tolerance can no longer meet high-performance applications. QFPCB uses advanced materials, manufacturing processes and quality control systems to achieve industry-leading ±5% impedance control and become a leader in high-end PCB manufacturing.
How to design high-speed PCBs with controlled impedance?
You should follow the below-mentioned controlled impedance routing tactics for designing a PCB:
Determine Which Signals Require Controlled Impedance
Most of the time, electronic engineers will specify which signal nets require specific controlled impedance. However, if not, the designer should look at the datasheet of the integrated circuit to determine which signals require controlled impedance. The datasheet will usually provide detailed guidelines for each group of signals and their impedance values. Spacing rules and information about which layer to route specific signals on may also appear in the datasheet or application notes. DDR traces, HDMI traces, Gigabit Ethernet traces, RF signals are some examples of controlled impedance traces.
Annotate the schematic with impedance requirements
The design of a board starts with the design of the circuit schematics by the design engineer. The engineer must specify controlled impedance signals in the schematic and classify specific nets to be either differential pairs (100Ω, 90Ω or 85Ω) or single-ended nets (40Ω, 50Ω, 55Ω, 60 Ω or 75Ω). It’s a good design practice to add N or P polarity indication after the net names of the differential pair signals in a schematic. The engineer should also specify particular controlled impedance layout design guidelines (if any) to be followed by the layout designer, either in the schematic or in a separate “Read Me” file.
Determine the trace parameters for controlled impedance
A PCB trace is defined by its thickness, height, width, and dielectric constant (Er) of the PCB material on which the traces are etched. While designing controlled impedance PCBs, it is essential to take care of these parameters. You can provide the manufacturer with the number of layers, the value of the impedance traces on specific layers (50Ω, 100Ω on Top layer or layer 3 ), and materials for PCB designing.
The manufacturer gives you the stack-up that mentions the trace widths on each layer, the number of layers, the thickness of each dielectric in the stack-up, trace thickness, and PCB material. He also takes care of the controlled impedance requirements by calculating the feasible thickness, width, and height for the traces that need impedance control. Stick to the following relationships to know how impedance depends on dimensions:
- Impedance is inversely proportional to trace width and trace thickness.
- Impedance is proportional to the laminate height and it is inversely proportional to the square root of laminate’s dielectric constant (Er).
Avoid these routing mistakes when designing for controlled impedance
Differentiate CI traces from other traces
The controlled impedance trace widths must be distinguishable from the remaining traces on the board. It allows the PCB manufacturer to quickly identify them and make suitable changes to the trace width if necessary, to achieve a specific impedance. For example, if you require a 5mil trace to achieve 50Ω impedance and if you have also routed other signals with 5mils width, it will be impossible for the PCB manufacturer to determine which ones are the controlled impedance traces. Therefore, you should make the 50Ω impedance traces 5.1mils or 4.9mils wide.
The table below shows trace widths and spacings for controlled impedance on different layers. Non-impedance signal traces should not be routed with 3.5, 3.6, 4.2, 4.25, and 4.3mil trace widths.
Maintain symmetry in differential pair routing
High-speed differential pair signal traces need to be routed parallel to each other with a constant spacing between them. The specific trace width and the spacing are required to calculate the particular differential impedance. The differential pairs need to be routed symmetrically. You should minimize areas where the specified spacing is enlarged due to pads or the ends.
Adequate spacing b/w controlled impedance traces, other traces, and components (3W and 2W rule) To reduce crosstalk, the spacing b/w traces should be 3W or at minimum 2W. Note that this rule does not apply to the spacing b/w differential pairs.
Placement of components, vias, and coupling capacitors
Components or vias should not be placed between differential pairs, even if the signals are routed symmetrically around them. Components and vias create a discontinuity in impedance and could lead to signal integrity problems. For high-speed signals, the spacing between one differential pair and an adjacent differential pair should not be less than five times the width of the trace (5W). You should also maintain a keep-out of 30mils to any other signals. For clocks or periodic signals, you should increase the keep-out to 50mils to ensure proper isolation.
If high-speed differential pairs require serial coupling capacitors, they need to be placed symmetrically, as shown in the below figure. The caps create impedance discontinuities, so placing them symmetrically will reduce the amount of discontinuity in the signal.
You should minimize the use of vias for differential pairs, and if you do place them, they need to be symmetrical to minimize discontinuity.
Length matching
Length matching will achieve propagation delay matching if the speed of the signals on various traces is the same. Length matching may be required when a group of high-speed signals travel together and are expected to reach their destination simultaneously (within a specified mismatch tolerance).
The lengths of the traces forming a differential pair need to be matched very closely; otherwise, that would lead to an unacceptable delay skew (mismatch between the positive and negative signals). The mismatch in length needs to be compensated by using serpentines in the shorter trace. The geometry of serpentine traces needs to be carefully chosen to reduce impedance discontinuity. The figure below shows the requirements for ideal serpentine traces. Read our post on how we manufacture controlled impedance PCBs.
The serpentine traces should be placed as near as possible to the source of mismatch. It ensures the mismatch correction as soon as possible. In the figure below, you can see that the mismatch occurs on the left set of vias, so the serpentine needs to be added on the left rather than on the right.
Similarly, bends cause mismatching making the trace on the inner bend smaller than the outer trace. Therefore, we need to add serpentines as close to the bend area. If a pair has two bends closer than 15mm, they compensate each other. Hence you do not need to add serpentines.
When a differential pair signal changes from one layer to another using vias and has a bend, each segment of the pair needs to be matched individually. Serpentines should be placed on the shorter traces near the bend. You need to manually inspect for this violation as it will not be caught in Design Rule Checks since the lengths of the total signals will be closely matched. Since the signal speed of traces on various layers may be different, it is recommended to route differential pair signals on the same layer if they require length matching.
Reference layers for the return path of controlled impedance signals
All high-speed signals require a continuous reference plane for the return path of the signal. An incorrect signal return path is one of the most common sources for noise coupling and EMI issues. The return current for high-speed signals closely follows the signal path, whereas the return current for low-speed signals takes the shortest path available. Generally, the return path for high-speed signals is provided in the reference planes nearest to the signal layer.
High-speed signals should not be routed over a split plane because the return path will not be able to follow the trace. You should route the trace around the split plane for better signal integrity. Also, make sure that the ground plane is a minimum of three times the trace width (3W rule) on each side.
If a signal needs to be routed over two different reference planes, a stitching capacitor between the two reference planes is required. The capacitor needs to be connected to the two reference planes and should be placed close to the signal path to keep the distance between the signal and the return path small. The capacitor allows the return current to travel from one reference plane to the other and minimizes impedance discontinuity. A good value for the stitching capacitor is between 10nF and 100nF.
You should avoid both split plane obstructions and slots in the reference plane just underneath the signal trace. If the slots are unavoidable, stitching vias should be used to minimize the issues created by the separated return path. Both pins of the capacitor should be connected to the ground layer and should be placed near the signal.
When vias are placed together, they create voids in reference planes. To minimize these large voids, you should stagger the vias to allow sufficient feed of the plane between vias. Staggering the vias allows the signal to have a continuous return path.
It is preferred to use ground planes for reference. However, if a power plane is used as a reference plane, you need to add a stitching capacitor to allow the signal to change the reference from the ground to the power plane and then back to the ground. You should place a capacitor close to the signal entry and exit points and connect one end to the ground and the other to the power net.
Add stitching vias close to the layer change vias
If a high-speed differential pair or single-ended signal switches layers, you should add stitching vias close to the layer change vias. This practice also allows the return current to change ground planes.
If a high-speed signal trace switches to a layer with a different net as reference, stitching capacitors are required to allow the return current to flow from the ground plane through the stitching capacitor to the power plane. The placement of the capacitors should be symmetrical for differential pairs.
