Controlled impedance is not created by trace width alone. It is the result of the finished stackup, dielectric properties, copper geometry, reference-plane relationship and fabrication process working together. QFPCB reviews these variables before production so designers can resolve stackup or geometry conflicts before boards reach the manufacturing floor.
Send the target impedance, tolerance, controlled-net information and preferred stackup with your fabrication package. Our engineering team can review manufacturability, identify any proposed trace-width or spacing changes, plan impedance coupons when required and confirm the applicable verification method for your order.
What you can request
- Single-ended and differential controlled-impedance structures
- Microstrip, embedded microstrip, stripline and coplanar structures
- Stackup and trace-geometry review before fabrication
- Impedance coupon and TDR planning when required by the purchase specification
- Prototype-to-production documentation continuity
- Project-specific review of materials, copper weight, tolerance and test reporting
Capability note: impedance targets, tolerances, coupon design, test method and report delivery must be confirmed for the specific material, stackup, geometry, panel plan and order quantity. The values below are design examples, not universal manufacturing promises.
What Is an Impedance Control PCB?
An impedance control PCB is manufactured so specified transmission lines remain within an agreed impedance tolerance after fabrication. The PCB drawing or fabrication notes identify the target, tolerance and controlled structures. The manufacturer then evaluates the proposed stackup and geometry against real material and process conditions.
This matters because the impedance in the finished board may differ from a value calculated with nominal dielectric thickness or a generic material constant. Copper thickness after plating, etched conductor shape, resin content and actual layer spacing can all change the result. Controlled impedance therefore requires design intent, manufacturing review and an agreed verification plan—not just a number beside a trace.
When Does a PCB Need Controlled Impedance?
A PCB generally needs controlled impedance when an interconnect behaves as a transmission line and reflections could reduce signal integrity. The decision depends on signal rise time, interconnect length, topology, interface specification and acceptable loss or timing margin. Clock frequency alone is not a reliable threshold.
Common applications include high-speed digital interfaces, RF and microwave paths, antennas and feed lines, networking hardware, data acquisition, telecom equipment, automotive electronics and precision test systems. Follow the interface or reference-design requirement when it specifies an impedance. For a short or slow connection with adequate margin, adding an unnecessarily tight tolerance may increase cost without improving performance.
Common Impedance Targets and Transmission-Line Structures
The correct target comes from the applicable interface specification, PHY or controller documentation and system design. Values such as 25, 40, 45, 50, 60, 75, 85, 90, 100 and 120 ohms occur in real products, but they are not interchangeable design options. QFPCB needs the required target and tolerance for each controlled structure rather than an instruction to apply one value across the whole board.
25-40 Ohm Low-Impedance RF and Microwave Lines
Low-impedance single-ended lines can appear in selected RF power, matching, filter or device-launch networks. They are not a universal RF standard. Achieving a lower impedance generally requires a wider conductor, a smaller distance to the reference plane, a higher effective dielectric constant or a combination of these changes. Wide conductors and component pads can create transitions that require electromagnetic review. Follow the RF device reference design or simulation result instead of assigning 25-40 ohms to every microwave path.
50 Ohm RF, Microwave and General Single-Ended Lines
Fifty ohms is the most widely recognized single-ended RF target because many RF components, connectors, instruments and coaxial systems are designed around it. It is also used for selected high-speed single-ended signals. On a PCB, 50 ohms may be implemented as microstrip, grounded coplanar waveguide or stripline. Each structure requires a different relationship between trace width, copper thickness, dielectric thickness, Dk and nearby ground copper. QFPCB models the actual selected structure rather than applying one universal 50-ohm trace width.
75 Ohm Video, RF and Instrumentation Lines
Seventy-five-ohm single-ended routing is associated with selected analog video, broadcast, RF and instrumentation interfaces that connect to a 75-ohm cable or connector environment. The PCB section should preserve that interface target through launches and termination components. A trace width copied from a 50-ohm design will not produce 75 ohms on the same stackup. The applicable product specification should determine whether the controlled section extends across the entire route or only through a defined analog front end.
85 Ohm Differential PCI Express Lines
PCI Express board channels commonly use an 85-ohm differential design target, but the applicable PCIe generation, add-in-card or system specification controls the exact routing and compliance requirements. Pair width, intra-pair spacing, reference planes, connector launch, vias and coupling all influence the channel. Do not derive the differential value by simply doubling a single-ended value: coupling between the two conductors changes differential impedance. QFPCB should receive the required target, tolerance and controlled layers with the fabrication package.
90 Ohm Differential USB Lines
USB high-speed and SuperSpeed routing commonly uses a 90-ohm differential target, with each conductor often discussed as approximately 45 ohms in an uncoupled context. The allowed range and test conditions depend on the USB specification, connector, cable or PCB channel segment and device guidance. Maintain pair symmetry, a continuous reference plane and controlled spacing, and minimize unnecessary stubs or asymmetrical via transitions. State the governing USB version and controller requirement rather than publishing one tolerance for every USB 2.0, USB 3.x or USB Type-C design.
100 Ohm Differential DDR Clock, HDMI, Ethernet and LVDS Lines
One hundred ohms is a common differential target for several interface families, but the shared number does not make their routing rules identical. DDR data and address nets are normally single-ended and controller-specific, while selected DDR clock pairs may be specified as differential. HDMI TMDS, LVDS and many Ethernet-related PCB connections also use differential structures around 100 ohms. Their loss budgets, termination, skew, via and connector requirements differ, so QFPCB reviews each net class and reference stackup separately.
120 Ohm CAN Bus and 100-120 Ohm RS-485/RS-422 Lines
CAN systems commonly use a nominal 120-ohm differential cable and termination environment; each conductor is sometimes described as approximately 60 ohms to the reference environment. RS-485 and RS-422 systems commonly use differential interconnects in the approximate 100-120-ohm range, depending on the selected cable and transceiver guidance. On short, slower PCB connections, the signal-integrity requirement may differ from a long cable segment. Match the PCB route, connector, cable and termination strategy instead of assigning 120 ohms from the bus name alone.
Microstrip, Stripline, Coplanar and Differential Structures
Microstrip routes use an outer-layer conductor over a reference plane. Stripline places a conductor between reference planes. Grounded coplanar structures add adjacent ground copper, so the coplanar gap, ground-via treatment and underlying reference plane become part of the model. Differential pairs add conductor-to-conductor coupling to the calculation. The same nominal impedance can therefore require different trace widths on different layers or in different structures.
The tolerance shown in a generic reference chart should not be treated as a universal manufacturing requirement. QFPCB confirms the achievable tolerance after reviewing the interface requirement, material, finished stackup, copper, line structure, feature dimensions, coupon and test method.
What Determines PCB Trace Impedance?
Impedance is governed by interacting material and geometry variables. A calculator result is useful only when its inputs represent the intended finished construction. QFPCB therefore reviews the production stackup and finished conductor geometry rather than treating the nominal layout dimensions as the complete impedance specification.
Trace Width
Trace width is one of the strongest adjustable geometry inputs. For a given material, copper thickness and reference-plane distance, increasing the width generally lowers characteristic impedance; reducing the width generally raises it. The relevant value is the finished conductor width after imaging, plating and etching, not only the nominal width in the CAD file. Etched conductors also have a trapezoidal cross-section, so top and bottom widths can differ. For a differential pair, both trace width and intra-pair spacing must be modeled because changing either alters coupling and differential impedance.
QFPCB may propose a small controlled-width or spacing adjustment when the designer’s nominal geometry does not match the approved production stackup. Any such change should remain limited to identified impedance structures and be approved before fabrication if it affects released design constraints.
Finished Copper Thickness
Copper thickness changes the conductor cross-section and therefore affects impedance. With the other variables fixed, increasing finished copper thickness generally lowers impedance. Outer layers require particular attention because the finished copper can include base foil plus subsequent plating, while inner layers are normally formed from a specified copper foil and etching process. Copper weight alone is not always a sufficient modeling input; QFPCB needs the intended base copper, plating condition and finished-copper assumption for each controlled layer.
Thicker copper also changes etch behavior and the achievable trace profile. A width calculated for nominal 1 oz copper cannot automatically be reused on a heavier-copper layer. The impedance model and manufacturing compensation must use the same finished geometry.
PCB Material Dielectric Constant (Dk)
The dielectric constant determines how strongly the electromagnetic field is concentrated in the PCB material. With geometry held constant, a higher effective Dk generally produces lower impedance, while a lower Dk generally produces higher impedance. The value needed for impedance modeling may not be the same as a generic catalog number: material datasheets can distinguish nominal, typical, specification and design Dk values, and the result depends on test method, frequency and laminate construction.
For microstrip, part of the field travels through air and part through the laminate, so the effective dielectric constant differs from the bulk material value. Resin content, glass weave and local construction can also influence the field. QFPCB confirms the material family, construction and modeling value before locking controlled trace geometry.
Solder Mask
Solder mask adds dielectric material above an outer-layer trace and changes the field distribution around a microstrip or coplanar structure. Covering a trace with solder mask generally lowers its impedance compared with the same exposed trace, although the size of the shift depends on mask thickness, dielectric properties, trace geometry and coplanar ground spacing. The effect becomes more important for narrow traces, tight tolerances and structures whose fields extend strongly into the coating.
The fabrication drawing should state whether controlled outer-layer lines are solder-mask covered, selectively opened or fully exposed. QFPCB then models and tests the structure in the condition that represents the finished board. A calculation for an exposed trace should not be used unchanged after the route is covered with mask.
Dielectric Thickness to the Reference Plane
Dielectric thickness is the finished distance between the signal conductor and its reference plane. With trace width, copper thickness and Dk held constant, increasing this distance generally raises impedance; reducing it generally lowers impedance. It also changes how tightly the return current is coupled to the signal path. The relevant input is the pressed dielectric thickness in the production stackup, not simply the prepreg’s unpressed catalog thickness.
Pressed thickness depends on core or prepreg selection, resin content, copper distribution and lamination conditions. Different controlled layers can therefore require different widths even when they use the same target impedance. QFPCB reviews the complete symmetric stackup, calculates the controlled structures against the proposed pressed construction and confirms any geometry adjustment before production.
Stackup Planning Before Layout Release
The safest workflow is to agree on a manufacturable stackup before final routing. Share the layer count, finished thickness, copper requirements, target impedances, interface constraints and any preferred material family. QFPCB can review the proposed construction and return the geometry assumptions used for layout.
This review helps prevent a common late-stage conflict: the routed trace width fits the design rules, but the selected dielectric spacing or finished copper requires a different width to achieve the target. Locking the stackup and impedance table together reduces layout rework and makes later CAM review more predictable.
Example 6-Layer Impedance-Controlled PCB Stackup
This six-layer order gives both outer signal layers an adjacent ground reference and places one inner signal layer between planes. It is a practical starting point when routing density is moderate.
| Layer | Suggested function | Impedance and routing role |
|---|---|---|
| L1 | Top signal / components | Controlled microstrip referenced to L2 |
| L2 | Ground plane | Continuous reference for L1 and L3 |
| L3 | Inner signal | Controlled stripline between L2 and L4 |
| L4 | Power plane | Reference only where the plane is continuous and suitable |
| L5 | Ground plane | Continuous reference for L6 |
| L6 | Bottom signal / components | Controlled microstrip referenced to L5 |
Example 8-Layer Impedance-Controlled PCB Stackup
An eight-layer construction adds routing capacity while retaining adjacent reference planes for the main controlled-signal layers. The L4/L5 plane pair should be selected around the board’s power-distribution and return-path requirements.
| Layer | Suggested function | Impedance and routing role |
|---|---|---|
| L1 | Top signal / components | Controlled microstrip referenced to L2 |
| L2 | Ground plane | Reference for L1 and L3 |
| L3 | Inner signal | Controlled stripline between L2 and L4 |
| L4 | Power or ground plane | Continuous reference selected for L3 |
| L5 | Power or ground plane | Continuous reference selected for L6 |
| L6 | Inner signal | Controlled stripline between L5 and L7 |
| L7 | Ground plane | Reference for L6 and L8 |
| L8 | Bottom signal / components | Controlled microstrip referenced to L7 |
Example 10-Layer Impedance-Controlled PCB Stackup
This ten-layer concept provides two internal signal layers enclosed by ground references, outer signal layers next to ground, and a central plane pair. It suits denser high-speed designs that benefit from stronger return-path control and additional routing capacity.
| Layer | Suggested function | Impedance and routing role |
|---|---|---|
| L1 | Top signal / components | Controlled microstrip referenced to L2 |
| L2 | Ground plane | Reference for L1 and L3 |
| L3 | High-speed inner signal | Ground-referenced stripline between L2 and L4 |
| L4 | Ground plane | Continuous second reference for L3 |
| L5 | Power plane | One side of the central plane pair |
| L6 | Power or ground plane | Second side of the central plane pair |
| L7 | Ground plane | Continuous first reference for L8 |
| L8 | High-speed inner signal | Ground-referenced stripline between L7 and L9 |
| L9 | Ground plane | Reference for L8 and L10 |
| L10 | Bottom signal / components | Controlled microstrip referenced to L9 |
These are layer-order examples, not finished impedance recipes. Final prepreg/core thicknesses, copper weights, resin content, material Dk, trace width, differential spacing and finished board thickness must be modeled together. Keep copper distribution and dielectric construction reasonably symmetric around the board centerline to reduce bow and twist. A power plane should serve as a high-speed reference only when it is continuous for the route and its return path is deliberately managed; do not route a controlled line across a plane split.
QFPCB Controlled Impedance Manufacturing Workflow
- Requirement review: We check the fabrication drawing, impedance table, stackup, controlled-net data and applicable tolerances.
- Construction review: Engineering evaluates material availability, pressed dielectric thickness, copper and the requested finished board thickness.
- Impedance modeling: The proposed transmission-line structures are modeled using the reviewed construction.
- DFM feedback: Any recommended trace-width, spacing or stackup change is returned for customer approval when it affects released data.
- Coupon and panel planning: A representative coupon is added when required and feasible for the order specification.
- Fabrication controls: Imaging, lamination, plating and etching are managed against the approved build.
- Verification and records: The agreed impedance test and reporting requirements are completed together with the order’s standard electrical inspection.
This workflow separates design assumptions from released manufacturing values. It also establishes who approves geometry changes before production starts.
Trace-Width Adjustment, Etch Compensation and Customer Approval
Yes, a fabricator may need to propose a controlled change to trace width or differential spacing. The designer’s geometry may have been calculated with nominal inputs, while the fabricator must account for the selected material construction, copper build and etching process. However, an impedance-related CAM change should not silently alter unrelated routing, clearances or electrical intent.
Define the approval boundary in the purchase data. QFPCB recommends identifying controlled nets and providing an impedance table so proposed changes can be reviewed against a clear requirement. If geometry cannot be changed, say so at quotation and provide the permitted stackup or material alternatives.
TDR Coupons, Testing and Impedance Reports
Time-domain reflectometry (TDR) is commonly used to evaluate controlled-impedance coupons. A coupon is designed to represent selected production structures and is placed on the manufacturing panel. The test launches a fast edge into the coupon and evaluates the reflected response along the line.
Coupon TDR does not replace bare-board continuity and isolation testing, and it does not automatically prove every routed segment on the finished PCB. It verifies the representative structures defined by the coupon and test plan. For insertion loss, return loss or high-frequency material characterization, additional methods may be required. Specify whether you need coupon results, a formal report, test frequency conditions or other acceptance records at RFQ stage.
Impedance Tolerance: How to Choose a Realistic Requirement
Choose tolerance from the interface budget and product risk, then confirm that the proposed stackup, geometry and verification method can support it. A tighter number is not automatically a better requirement. It may restrict material or geometry choices, require more process control and testing, and increase cost or lead time.
As a common RFQ starting point, designers often discuss ±10% and tighter requirements such as ±5%, but neither should be treated as a universal QFPCB capability or the correct value for every structure. QFPCB confirms the achievable tolerance after reviewing the material, layer construction, copper, line type, feature dimensions and test plan.
Design and DFM Checks for Controlled Impedance Traces
- Route over a continuous reference plane and avoid crossing plane splits or voids.
- Keep the stackup, impedance table and layout design rules synchronized.
- Maintain differential-pair geometry through routing changes; minimize unnecessary discontinuities.
- Review connector launches, vias, pads, neck-down regions and layer transitions as part of the signal path.
- Keep unrelated copper and components far enough from modeled structures, especially for coplanar routing.
- Define whether outer-layer traces are modeled with solder mask.
- Use smooth, intentional geometry transitions and limit uncontrolled stubs.
- Obtain approval before changing controlled trace widths or pair spacing in CAM.
Fabrication impedance control cannot correct every discontinuity in the product. Connector selection, via design, return-path transitions and package breakouts remain system-level signal-integrity decisions.
Common Impedance Control Problems and How to Prevent Them
| Problem | Likely cause | Prevention |
|---|---|---|
| Calculated width conflicts with fabrication stackup | Nominal or generic material inputs | Approve the production stackup before final routing |
| Ambiguous controlled nets | Target appears only in an email or net name | Add a controlled-impedance table and identify layers/nets |
| Pair geometry changes unexpectedly | No CAM-change approval rule | State permitted changes and require approval |
| Test record does not match expectation | Coupon/report requirement omitted from RFQ | Define coupon, acceptance and report needs before quoting |
Files Required for a Controlled Impedance PCB Quote
Provide a complete, internally consistent package. At minimum, include:
- Gerber or ODB++ fabrication data and NC drill files
- Fabrication drawing with layer order, finished thickness and copper requirements
- Stackup proposal or request for a manufacturer-proposed stackup
- Impedance table listing target, tolerance, layer, structure and reference plane
- Controlled-net report or clear net/feature identification
- Differential-pair width and spacing constraints where applicable
- Material preference and whether approved alternatives are allowed
- Solder mask condition for outer-layer controlled lines
- Panel, coupon, TDR report and other inspection requirements
- Quantity, delivery target and applicable standards or customer specifications
If the same target appears on several layers, list each structure separately. Different dielectric spacing or copper conditions can require different geometry even when the target impedance is identical.
Controlled Impedance PCB FAQ
Is impedance control necessary if I already calculated the trace width?
It may still be necessary. Your calculation describes a design based on assumed inputs, while the fabricator must build and verify a finished stackup using actual material constructions and process allowances. Submit the target, tolerance and controlled nets—not only the width—so the manufacturer can compare your geometry with the proposed production stackup.
Should a PCB manufacturer be allowed to change trace width or differential spacing?
Only within an agreed approval process. A manufacturer may propose geometry changes to compensate for the production stackup, copper build or etching, but the change can affect routing clearance and coupling. State what may be adjusted and require approval of revised controlled widths, spacing or stackup before fabrication.
What is the difference between controlled impedance and controlled dielectric?
Controlled impedance specifies the electrical result for a transmission-line structure. Controlled dielectric focuses on maintaining a defined dielectric thickness or construction so the designer’s fixed geometry produces the intended result. The appropriate method depends on design ownership, stackup maturity and procurement requirements; confirm the approach with the fabricator before layout release.
How is 50-ohm PCB impedance tested?
It is commonly checked with TDR on a representative coupon built on the same production panel. The approved test plan defines the coupon structure, target and tolerance. TDR coupon testing is distinct from routine continuity and isolation testing, and additional RF measurements may be needed when loss or frequency-domain behavior is an acceptance requirement.
What is a PCB impedance test coupon?
An impedance coupon is a panel feature containing transmission lines designed to represent selected structures on the production PCB. It gives the fabricator an accessible test vehicle for TDR measurement. Because a coupon represents defined structures rather than every routed feature, its layer, geometry, reference planes and location must align with the verification plan.
Is ±10% impedance tolerance enough, or do I need ±5%?
Use the tolerance required by the interface and signal-integrity budget. ±10% is a common discussion point, while ±5% is tighter and may require greater constraints on material, geometry and process. Neither is automatically correct. Ask QFPCB to review the exact stackup and test plan before treating a tolerance as manufacturable.
Can one PCB contain several controlled impedance values?
Yes. A board can contain multiple single-ended and differential targets across different layers. Each unique structure should be listed separately because layer spacing, copper thickness, solder mask and coupling may change the required geometry. The fabrication drawing should link every target to its layer, reference plane, line type and controlled nets.
What information should be included in an impedance table?
List the target impedance, tolerance, layer, single-ended or differential structure, trace width and pair spacing constraints, reference plane, and controlled-net identification. Also identify the approved stackup revision and solder mask condition. This gives the fabricator enough context to model the intended structure and flag conflicts before production.
Does an impedance test replace PCB electrical testing?
No. Impedance testing evaluates the transmission-line characteristic defined by the coupon or test structure. Bare-board electrical testing checks continuity and isolation for the board’s conductive network. A controlled-impedance order may require both, plus other inspections or RF measurements depending on the product specification.
Request an Impedance and Stackup Review
Send QFPCB your fabrication package, target impedance table, preferred stackup and quantity. We will review the construction, controlled geometry, tolerance and verification requirements before quotation. If a trace-width, spacing, material or layer-thickness change is recommended, the proposal can be returned for approval before production.
Recommended CTA: Upload your PCB files and request a controlled impedance stackup review.