IC Substrate - QFPCB Printed Circuit Board and PCBA manufacturing

IC Substrate Manufacturer for Fine-Line Package Boards

IC package substrates need more than a smaller version of ordinary PCB design rules. Thin cores, fine copper patterns, small laser vias, tight registration and package-side finish requirements interact. A design can meet each nominal limit separately and still be difficult to manufacture when those limits occur in the same area.

QFPCB supports engineering review and manufacturing for organic IC substrates using listed BT and related core/prepreg systems, subtractive or mSAP patterning, and project-specific stackup planning. The current general process window includes 1-16 layers, 30/30 µm minimum line and space, 80 µm minimum pads, 250 µm minimum BGA center spacing and 50 µm minimum laser holes. Every project remains subject to material, stackup, feature-combination and acceptance-criteria review.

Planning an IC substrate build? Send the package drawing, Gerber or ODB++ data, stackup, material preference, via map, finish requirement and forecast volume. QFPCB can review the risk-driving features before quotation.

Send Files for Engineering Review

IC Substrate Manufacturing Capabilities at a Glance

The values below are general capability windows taken from QFPCB’s current IC substrate process table. They are not a universal design rule. Minimum pattern, via, registration, thickness and solder mask limits may require different process margins and may not be available together.

Capability item	General window	Engineering note
Layer count	1-16 layers	Stackups above eight layers require project-specific thickness planning.
Minimum line / space	30 / 30 µm	Confirm the fine-line area, copper thickness and selected pattern process.
Minimum pad	80 µm	Pad finish, solder mask opening and inspection method must be reviewed together.
Minimum BGA center spacing	250 µm	Provide the package land map and escape-routing area for review.
Minimum laser hole	50 µm	Via diameter alone does not define feasibility; dielectric thickness, land and fill are also required.
Minimum mechanical hole	100 µm	Confirm drill method, finished-hole definition, land size and thickness relationship.
Pattern processes	Subtractive and mSAP	Process selection depends on line width, copper distribution, thickness and production plan.

What an IC Substrate Does Between the Die and the PCB

An IC substrate is the high-density interconnect between a semiconductor die and the system PCB. It redistributes dense die-side connections to a larger package-side pattern, supports the die mechanically and provides paths for power, ground and signals. Depending on the package architecture, the substrate may also influence heat flow, warpage, assembly yield and electrical performance.

That role explains why an IC package substrate cannot be specified by layer count and outline alone. The manufacturer needs to understand the die connection method, package land pattern, routing density, power distribution, via structure, material system, surface finish and assembly sequence. A drawing that omits one of these interfaces can move risk into fabrication or package assembly.

The page is intended for organic package-substrate projects within the confirmed process window. It does not claim semiconductor wafer fabrication, die attach, bumping, wire bonding, molding or complete OSAT packaging unless those services are separately confirmed for the project.

IC Substrate Types and Where the Capability Fits

IC substrates are often described by package architecture or connection method. Common search terms include BGA substrate, CSP substrate, FCCSP substrate, FCBGA substrate, wire-bond substrate and SiP substrate. These labels are useful, but they do not automatically define a manufacturable construction.

Wire-bond substrates route from die-side bond fingers to package-side lands. Finger geometry, finish, contamination control and bondability criteria must be stated.
Flip-chip substrates connect the die through a bump array. They generally place stronger demands on pad pitch, escape routing, layer registration, microvias and warpage control.
CSP and FCCSP substrates emphasize compact outlines and fine routing. The package drawing and bump map should be reviewed before the stackup is frozen.
BGA and PBGA substrates may use BT-based materials, but the exact laminate, glass style and resin system depend on thickness, reliability and assembly needs.
SiP and module substrates can combine RF, digital, memory or passive functions. Mixed routing and local copper density make early stackup and finish review especially important.

QFPCB should not be selected only because a generic package name appears on a capability list. The more reliable approach is to compare the actual design feature map with the available material and process window.

BT and Related Material Options for Package Substrates

The current capability source lists core and prepreg families from Shengyi, Mitsubishi Gas Chemical, Doosan, Panasonic and other suppliers. Listed series include SI643HU, SI10US, SI09U, SI07U, SI05U, HL832NXA, HL832NS, HL832NSR(LC), DS-7409HGB variants, R1515E, R1515H, E679FGB, E770G(LH) and BT-NSF(LCA).

This list is a starting point for engineering review, not a statement that every grade is always in stock. Exact datasheet revision, copper type, dielectric thickness, resin content, glass style, dimensional behavior, surface quality and minimum purchase quantity must be confirmed when the quotation is prepared.

Decision field	What to provide	Why it changes the build
Material grade	Exact supplier series or acceptable alternatives	Controls sourcing, dielectric construction and process compatibility.
Thickness system	Total thickness, core, prepreg and copper by layer	Affects rigidity, warpage, laser-via geometry and registration margin.
Thermal profile	Assembly peak, cycles and reliability conditioning	Links material choice to dimensional stability and interconnect reliability.
Electrical targets	Impedance, insertion loss or power-integrity constraints	Determines whether dielectric data and copper geometry need tighter control.

For a broader explanation of BT laminates, see QFPCB’s bismaleimide-triazine PCB material guide. Use that article for material education; use this service page for a manufacturability review and quotation.

Fine-Line Patterning: When to Use Subtractive Processing or mSAP

Subtractive processing starts with copper and removes unwanted areas by etching. It remains practical where the line/space geometry, copper thickness and tolerances provide enough process margin. As lines become narrower, lateral etching and copper-profile control become more influential.

mSAP uses a thin seed copper layer, patterned plating and flash etching to form finer conductors with less dependence on removing a thick base copper layer. This can help dense routing, but the process name alone does not guarantee a specific feature. Design feasibility still depends on dielectric surface, seed-layer formation, imaging, plating uniformity, flash-etch control, copper distribution and inspection.

QFPCB’s current table lists both subtractive and mSAP support and a general minimum pattern of 30/30 µm. The best process should be selected from the complete layer data rather than from the smallest line on the drawing. If only a small escape-routing region needs 30/30 µm while most traces are wider, identify that region clearly. Localizing the critical geometry can make engineering review more accurate.

The attachment does not list SAP, ETS or coreless capability. Those terms should not be added to a request or sales claim without a separate confirmation.

Thin Stackups, Microvias and Registration Need a Combined Review

The capability table provides minimum construction references of 80 µm for a two-layer substrate, 200 µm for four layers, 240 µm for six layers and 330 µm for eight layers. It also lists minimum core and prepreg values of 40 µm and 25 µm, plus a 50 µm minimum laser hole.

These numbers are not interchangeable building blocks. A minimum total thickness may use a different material set or copper balance than a construction using the minimum prepreg. Likewise, a 50 µm laser via needs a compatible dielectric thickness, land diameter, capture-pad tolerance, copper-fill plan and stacked or staggered via decision.

From a CAM review perspective, the important question is not “Can you make a 50 µm laser hole?” It is “Can this 50 µm via, on this dielectric thickness and land geometry, remain registered after lamination and meet the specified fill and reliability criteria?”

Designers should provide the via span for every microvia type, whether vias are stacked or staggered, the required copper fill, the pad and anti-pad sizes, and any via-in-pad conditions. If the design uses 10-16 layers, submit the complete proposed stackup because the source table does not provide minimum-thickness examples above eight layers.

Pads, Solder Mask and Surface Finish for Package Assembly

The listed general window includes an 80 µm minimum pad, 250 µm minimum BGA center spacing, 65 µm minimum finger center distance and 5 µm solder mask registration tolerance. These values influence one another. A pad may be manufacturable in copper but still need a larger solder mask opening, a different finish or a more conservative assembly tolerance.

Available finish categories in the source are soft gold plating, hard gold plating, ENIG and OSP. Choose by the real interface:

Soft gold may be relevant to a bonding requirement, but the plating stack and bondability acceptance criteria must be specified.
Hard gold is intended for wear or contact applications and should not be substituted for a bondable finish without approval.
ENIG offers a planar solderable surface, but nickel and gold thickness and package reliability requirements need confirmation.
OSP provides a thin copper-protection finish and requires agreement on handling, storage and assembly exposure.

The attachment does not list ENEPIG even though other QFPCB product examples may use it. A design that requires ENEPIG should be quoted as a separate finish requirement rather than silently mapped to the attachment.

Solder resist families listed are EG23A, AUS308, AUS320 and AUS410, with green and black as listed colors. Color, material family, opening geometry, final thickness and curing requirements should be locked together. The capability table specifies 5 µm maximum flatness; the project drawing should also state the measurement method, conditioning state, substrate size and sampling plan.

DFM Review Before Releasing an IC Substrate Design

A useful IC substrate DFM review checks the complete tolerance chain instead of comparing a few minimum values with a capability chart. QFPCB’s review should cover:

Package interface: die bump or bond-finger map, package-side lands, component keep-outs and datum strategy.
Stackup: material grade, dielectric and copper thickness by layer, build-up sequence, total thickness and tolerance.
Pattern density: minimum line/space locations, neck-down length, copper balance and isolated versus dense features.
Via structure: mechanical and laser hole sizes, lands, spans, stacked/staggered arrangement, fill and planarization.
Registration: layer-to-layer targets, pad capture, solder mask opening and routing-to-edge tolerance.
Finish: soldering, wire bonding or contact function, thickness requirement and inspection method.
Reliability: thermal cycles, moisture conditioning, warpage or flatness requirement and electrical test criteria.
Panel and volume: substrate outline, array format, tooling features, sample quantity and forecast production demand.

An early review is especially important when the drawing combines minimum line/space, minimum pads, minimum laser vias and a minimum total thickness. Asking for approval after routing is complete can force a material or geometry change that affects the package escape plan.

Quality Controls and Acceptance Criteria to Define

Fine-line package substrates need inspection criteria that match the design risks. The exact quality plan should be agreed during quotation, but common control points include incoming material verification, artwork and impedance review where applicable, lamination registration, laser-via formation, copper plating and fill, pattern inspection, solder mask registration, finish verification, profile measurement and electrical testing.

Do not rely on the phrase “100% tested” without defining the test. State whether the order requires netlist electrical test, continuity/isolation thresholds, impedance coupons, microsection sampling, surface-finish thickness, dimensional inspection, warpage or flatness measurement, ionic cleanliness, thermal stress or another package-specific reliability plan.

Acceptance criteria should identify the governing drawing and revision. If an IPC, JEDEC, customer or internal specification applies, include the exact document and class or test condition. QFPCB should confirm which criteria can be supported before fabrication begins rather than after finished substrates are available.

Files Required for an IC Substrate Quotation

Send a complete data set whenever possible. A partial Gerber package can support an early feasibility discussion, but it is not enough for a reliable production quotation.

Gerber X2, ODB++ or IPC-2581 fabrication data;
NC drill and laser-via data with via spans identified;
package outline and dimensioned fabrication drawing;
die-side bump map or wire-bond finger drawing;
package-side BGA, LGA or other land pattern;
proposed stackup with material grades and copper thicknesses;
solder mask openings and required resist family or performance;
surface finish, plating thickness and bonding or soldering requirement;
impedance or electrical constraints, if applicable;
array/panel drawing, fiducials and tooling requirements;
inspection, reliability and acceptance specifications;
prototype quantity, annual forecast and target schedule.

If the material is not fixed, provide the reason behind the selection: package thickness, reflow warpage, fine-line routing, moisture performance, electrical loss or supply-chain constraint. That information helps engineering evaluate an alternative without changing the real design objective.

From Prototype Review to Repeat Production

Prototype approval should confirm more than electrical continuity. Review dimensional results, microvia and plating evidence, critical line geometry, solder mask registration, surface finish, outline, flatness or warpage criteria and assembly feedback. Record the approved material revision, stackup, tooling and inspection plan so repeat builds do not depend on informal assumptions.

When moving toward production, identify which features control yield and which substitutions require approval. A nominally equivalent core or prepreg may change dielectric thickness, glass construction, dimensional behavior or lamination response. A finish change may affect assembly or bonding. A panel change can alter copper distribution and dimensional compensation.

QFPCB can support the transition by reviewing fabrication data, clarifying stackup and process choices, documenting open engineering questions and aligning the quotation with the requested inspection plan. Production availability, lead time and volume capacity should be confirmed for the exact material and construction.

Why Work With QFPCB on an IC Substrate Project

QFPCB’s useful role is to turn a package-substrate drawing into a manufacturable process plan within a confirmed capability window. The current baseline combines listed BT and related material families, subtractive and mSAP patterning, thin multilayer references, laser microvias, fine pads and multiple finish options.

The engineering value comes from identifying feature combinations that need review before the design is released. Instead of assuming every published minimum can be used together, QFPCB can check the package map, stackup, material, line/space distribution, via structure, solder mask, finish and acceptance criteria as one system.

For adjacent capabilities, see PCB Manufacturing, HDI PCB and High Frequency PCB. These pages describe related processes but do not replace an IC substrate design review.

Frequently Asked Questions About IC Substrates

What is the difference between an IC substrate and a PCB?

An IC substrate connects the semiconductor die or package interface to the larger system PCB using much finer routing, thinner dielectric structures and tighter registration. A conventional PCB connects packaged components at board level. The two use related manufacturing concepts, but an IC substrate normally requires package-specific pad maps, microvias, materials, finishes and tolerance control.

What information does an IC substrate manufacturer need for a quote?

Provide the fabrication data, package outline, die-side and package-side land maps, stackup, material preference, copper thickness, via spans, solder mask, finish, inspection criteria, quantity and forecast volume. If the material is open, explain the thermal, electrical, thickness or reliability target so the manufacturer can review alternatives without changing the package objective.

Can QFPCB manufacture 30/30 µm line and space on every IC substrate?

No. The 30/30 µm value is a general minimum process window, not a preferred rule for every layer or construction. Feasibility depends on copper thickness, pattern density, material surface, process choice, registration, total thickness and the other minimum features used nearby. Submit the critical layers and feature map for a combined CAM review.

When should mSAP be used for an IC package substrate?

mSAP is worth reviewing when fine routing or tighter conductor control is difficult with the planned subtractive copper process. The decision should use the actual line/space map, copper thickness, dielectric surface, production quantity and inspection plan. A project does not automatically need mSAP simply because it is called an IC substrate or includes one small fine-line area.

Which materials are available for BT IC substrates?

QFPCB’s current capability source lists Shengyi SI-series materials, Mitsubishi Gas Chemical HL832 series, Doosan DS-7409HGB variants, Panasonic R1515E/R1515H and additional E679FGB, E770G(LH) and BT-NSF(LCA) options. Availability and exact datasheet revision must be confirmed for each order because the list does not mean every grade and thickness is continuously stocked.

What is the minimum laser-via size for an IC substrate?

The current general capability table lists a 50 µm minimum laser hole. That number cannot be evaluated alone. The manufacturer also needs dielectric thickness, capture and target pad sizes, via span, stacked or staggered construction, copper-fill requirement and registration tolerance. The complete via structure must pass engineering review before it becomes an order specification.

Which surface finish should be used on an IC substrate?

Choose the finish from the assembly interface. The current list includes soft gold, hard gold, ENIG and OSP. Wire bonding, soldering and wear contacts have different plating and reliability needs, so one finish should not be substituted for another by name alone. State the function, thickness requirement, bonding or soldering process and acceptance test in the quotation package.

Can the minimum thickness, 30/30 µm routing and 50 µm laser vias be combined?

Not automatically. Published minima are usually established under particular materials and process conditions. Combining minimum total thickness, fine routing, small vias, tight solder mask registration and demanding flatness can reduce process margin. QFPCB should review the complete stackup and critical-feature map, then confirm which limits can coexist and where design relaxation is advisable.

Does QFPCB support 16-layer IC substrates?

The current capability table lists 1-16 layers. However, its minimum-thickness examples stop at eight layers, so a 10-16-layer design needs a project-specific stackup review. Provide the material system, build-up sequence, copper thicknesses, total thickness, via spans, registration targets and reliability requirements before treating the layer-count range as a confirmed construction.

How should flatness or warpage be specified for an IC substrate?

The current capability table specifies 5 µm maximum flatness. A quotation should still define the measurement method, temperature or conditioning state, substrate size and sampling plan because the numeric value alone does not establish an acceptance procedure. The project drawing and agreed inspection method should control manufacturing and final acceptance.

Request an IC Substrate Engineering Review

Send QFPCB your package drawing, fabrication data, stackup, material requirement, via map, finish specification, inspection criteria and order forecast. Engineering will compare the design against the confirmed process window and identify questions involving fine lines, microvias, registration, thin construction, material or package-side assembly before quotation.

Contact QFPCB About Your IC Substrate Project