Controlled impedance plays a crucial role in the Printed circuit board’s performance. Impedance control with manual calculations, and designing software aids in many ways to keep the design and development under control. Altium software has features to load the parameters required for designing, manufacturing, and setting the rules which are also customizable to layers. Altium also helps design the layer stack up, routing for impedance control. The signal integrity tool in Altium assists in simulating the noise reflections. Routing impedance is majorly dependent on the dimensions of the copper trace and the return path/ ground path with dielectric properties, thickness, and copper thickness. Copper orientation and surface roughness of these traces can also be set with the features available in Altium Designer. This article will analyze the Altium controlled impedance in detail, hoping to help you.
Impedance Control in Routing
Routing the traces becomes a critical part of the Printed circuit board operation for high-frequency circuit components abiding by the manufacturing capability norms. The characteristic impedance Z0 of a trace is treated as a part of the component. To manage the impedance control, various external components are added and trace impedance is kept under control while routing is called impedance control routing.
Altium controlled impedance of the routing is calculated by 3 major factors which are also shown in the Altium’s property tab:
- The cross-section of the trace is calculated using the Altium tool with the following parameters as shown in the image below. The upper width of the trace, lower width of the trace, and trace height.
- Return path to signal trace as the return path travels back to the source as the signal path in the ground plane.
- Energy in the copper trace does not just travel through the trace but on the surface of the trace due to the skin effect. The energy inside a PB travels through the field so the material property of the dielectric is important to determine the flow of energy.
Impedance Matching Using Components in Altium
Impedance matching with component selection is also crucial as the components internally have a certain impedance. The component impedance will combine with the trace impedance and impact effectively on the circuit impedance in total. Therefore, matching component impedance plays a major role. This is achieved using signal integrity in the tools menu in Altium designer software; where the errors and warnings will occur in the pop-up box. This contains major features, which are assigning model assignments to simulate and conclude the signal integrity.
Analyzing Using Altium
- Clicking on the tools >> Signal integrity on the main menu bar helps to simulate and analyze the designs.
- The signal integrity tab shows the Net labels, Status of signal integrity, falling edge over, falling edge under, rising edge over, rising edge under.
- The time stamps assist the designer in working on the signal routing. The netlabel can be cross-probed by right-clicking on the particular netlabel and to control the impedance.
- Theoretical termination can be enabled for multiple nets with signified values for it.
- Termination types can be opted from the following for better output and the one which can be adapted for the application
- Series resistance
- Parallel resistor to VCC
- Parallel resistor to GND
- Parallel capacitor to ground
- Resistor and Capacitor to GND
- Parallel Schottky diodes
- After selecting one or more suggestions the nets are simulated with waves and the reflection of waves is shown in the results in a new window.
- All the nets that are in the main menu will be analyzed; At the bottom of the window, the nets can be selected to view the waveforms in the primary graph which depicts the signal behavior.
- The secondary graph shows all six termination options according to the sweeps that we selected from the termination. The First sweep represents without termination and rest 5 sweeps show the signal after termination results
- Based on the output sweeps the design can be adapted to perform with reliable signal integrity.
The below image shows an example of bad signal integrity results with reflections causing spikes on the rising edge and falling edge.
The image below shows the result of the noisy line after opting for the termination value and connecting with the appropriate connection.
Configuration of Controlled Impedance in Altium
Altium Controlled impedance is setting the values of the PCB with the PCB editors layer stack manager. Layer stack determines the impedance as the return path plays a major role. If the distance between the signal and reference plane is more, then the impedance will be high. Major steps of Altium impedance controll that need to be configured are listed below.
- In the main menu bar clicking Design >> Layer stack up manager will pop up a window. The sheet has an impedance tab that can be configured.
- The target Impedance, target tolerance, and copper surface roughness can be set in this tab.
- In the stack-up layer, the thickness of the signal layer, the thickness of the dielectric, the dissipation factor (Df), and the dielectric permittivity (Dk) are set to the values in the suggested configuration.
- When the suggested configuration is set, the toll shall be able to calculate the appropriate following results.
- (W) – Trace width
- (Zcomm) – Common mode impedance
- (Z) – Calculated Impedance
- (Z Deviation) – Impedance deviation
- (Tp) – Propagation delay
- (P.U.I) – Inductance per unit length
- Capacitance per unit length
The below image shows the layer stack up impedance configuration tab with results of the line that are shown on the right side under the layer stack up manager tab.
- We can set a new Altium impedance controll profile by clicking the “Add impedance profile” button
- This shows the type of impedance, target impedance, and target tolerance which are the main properties
- Individual copper layers selected on the check box are analyzed for Altium impedance controll calculations
- Only the enabled layers are highlighted when clicking on the profile regions with top and bottom reference columns.
- The copper layers can be either complete plane or signal layers. Each layer can be set with its reference layer
- Finally enabling the impedance profile check box for every layer will design routing according to the impedance.
- Tuning with gap settings contains the tech factor value, top width, bottom width, impedance of the trace, deviation, delay, inductance, and capacitance based on the fabricator’s profile
- Copper layer orientation can be set if the transmission layer needs to be up or by selecting the inverted check box the toggle option is enabled.
- The conductor surface roughness factor plays a major role in improving the adhesion between the copper layer and dielectric/prepreg substrate. The conductor surface can increase the impedance of the signal lines carrying over a rate of 10 GB per second. Characteristic Altium impedance controll factor consists of surface roughness on the tab
- Roughness can be selected with the model type, surface roughness within the micrometer range, and roughness factor defined from 1 to 100 constant numbers.
- The coplanar transmission line option is to set the inter distance between the signal lines that is nothing but clearance which keeps away impedance from other lines.
- These parameters are set for differential pair routing, shielding specific defined net values, via stitching, and copper shield option around the net as shown in the image below.
- Custom materials can be added to the material library in the Altium material library option for the dielectric property, if we are using standard dielectric material then it can be chosen from the default menu dropdown.
- Stack-up can be kept symmetrical which will enable equal Altium controlled impedance on both sides of the board.
Configuring the Design Rules in Altium
The design rules can be configured by selecting Design >> Rules in the PCB rules and constraint manager.
- The trace width with minimum, max, and preferred widths can be configured with the user’s constraints
- Differential pair routing design can be edited with the preferred width and the preferred gap between the lines.
- For every signal like the reference or the ground plane can be set to ensure the routing does not traverse beyond as this controls the impedance. The violation can be set with min and max in DRC rules.
- Length tuning the routes to match the Altium controlled impedance profile can be set not just to match the length for differential pairs but also for high-speed signal routing or bus.
